MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 135

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.4.1 Address Attribute Trigger Register (AATR)
The address attribute trigger register (AATR) defines address attributes and a mask to be
matched in the trigger. The register value is compared with address attribute signals from
the processor’s local high-speed bus, as defined by the setting of the trigger definition
register (TDR).
Table 5-4 describes AATR fields
DRc[4–0]
Reset
0x0A–0x0B Reserved
0x01–0x04 Reserved
Field RM
DRc[4–0]
R/W Write only. AATR is accessible in supervisor mode as debug control register 0x06 using the WDEBUG
0x0C
0x0D
0x0E
0x0F
0x00
0x05
0x06
0x07
0x08
0x09
instruction and through the BDM port using the
15
Debug control registers can be written by the external
development system or the CPU through the WDEBUG
instruction.
CSR is write-only from the programming model. It can be read
or written through the BDM port using the
WDMREG
Configuration/status register
BDM address attribute register
Address attribute trigger register
Trigger definition register
Program counter breakpoint register
Program counter breakpoint mask register
Address breakpoint high register
Address breakpoint low register
Data breakpoint register
Data breakpoint mask register
Figure 5-5. Address Attribute Trigger Register (AATR)
14
SZM
13
commands.
Freescale Semiconductor, Inc.
Table 5-3. BDM/Breakpoint Registers
For More Information On This Product,
12
Register Name
TTM
11
.
Chapter 5. Debug Support
Go to: www.freescale.com
10
TMM
0000_0000_0000_0101
NOTE:
9
WDMREG
8
0x06
R
7
Abbreviation
command.
DBMR
PBMR
BAAR
ABHR
AATR
ABLR
CSR
DBR
TDR
PBR
—
—
6
SZ
5
RDMREG
0x0010_0000
0x0000_0005
0x0000_0005
0x0000_0000
Initial State
4
TT
—
—
—
—
—
—
—
—
Programming Model
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and
2
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