MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 192

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programming Model
6.2.10.1.1 Arbitration for Internally Generated Transfers (MPARK[PARK])
MPARK[PARK] prioritizes internal transfers, which can be initiated by the core and the
on-chip DMA module, which contains all four DMA channels. Priority among the four
DMA channels in the module is determined by the BWC bits in their respective DMA
control registers (see Chapter 12, “DMA Controller Module”).
The four arbitration schemes for internally generated transfers are described as follows:
6-12
Bits
2–1
3
0
• Round-robin scheme (PARK = 00)—Figure 6-10 shows round-robin arbitration
between the core and DMA module. Bus mastership alternates between the core and
DMA module.
The DMA module presents only the highest-priority DMA request, and bus
mastership alternates between the core and DMA channel as long as both are
requesting bus mastership. Section 12.5.4.1, “External Request and Acknowledge
Operation,” includes a timing diagram showing a lower-priority DMA transfer.
When the processor is initialized, the core has first priority. If DMA channels 0 and
1 (both set to BWC = 010) assert an internal bus request during a core-generated bus
transfer, DMA channel 0 would gain bus mastership next. However, if the core
requests the bus during this DMA transfer, bus mastership returns to the core rather
than being granted to DMA channel 1.
SHOWDATA Enable internal register data bus to be driven on external bus. EARBCTRL must be set for
BCR24BIT
Name
—
Table 6-6. MPARK Field Descriptions (Continued)
Figure 6-10. Round Robin Arbitration (PARK = 00)
this function to work. Section 6.2.10.1.2, “Arbitration between Internal and External Masters
for Accessing Internal Resources,” describes the proper use of SHOWDATA.
0 Do not drive internal register data bus values to external bus.
1 Drive internal register data bus values to external bus.
Reserved, should be cleared.
Controls the BCR and address mapping for DMA. Allows the BCR to be used as a 24-bit
register. Chapter 12, “DMA Controller Module,” describes the BCRs.
0 DMA BCRs function as 16-bit counters.
1 DMA BCRs function as 24-bit counters.
(Alternates between Core and DMA Module)
CORE
Freescale Semiconductor, Inc.
For More Information On This Product,
Internal Bus Mastership
Go to: www.freescale.com
5th
3rd
1st
MCF5307 User’s Manual
4th
2nd
Description
DMA MODULE
Channel 0
Channel 1
Channel 2
Channel 3