MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 183

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.2 Programming Model
The following sections describe the registers incorporated into the SIM.
6.2.1 SIM Register Memory Map
Table 6-1 shows the memory map for the SIM registers. The internal registers in the SIM
are memory-mapped registers offset from the MBAR address pointer defined in
MBAR[BA]. This supervisor-level register is described in Section 6.2.2, “Module Base
Address Register (MBAR).” Because SIM registers depend on the base address defined in
MBAR[BA], MBAR must be programmed before SIM registers can be accessed.
0x010–
MBAR
Offset
0x00C
0x03C
0x000
0x004
0x008
0x040
0x044
0x048
Default bus master park
Reset status register
PLL control (PLLCR)
register (MPARK)
Although external masters cannot access the MCF5307’s
on-chip memories or MBAR, they can access any of the SIM
memory map and peripheral registers, such as those belonging
to the interrupt controller, chip-select module, UARTs, timers,
DMA, and I
(RSR) [p. 6-5]
Pin assignment register (PAR) [p. 6-10]
[p. 6-11]
[31:24]
[p. 7-3]
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C.
Interrupt Control Registers (ICRs) [p. 9-3]
Interrupt Controller Registers [p. 9-2]
Table 6-1. SIM Registers
System protection
(SYPCR) [p. 6-8]
Chapter 6. SIM Overview
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control register
Interrupt pending register (IPR) [p. 9-6]
Interrupt mask register (IMR) [p. 9-6]
Reserved
[23:16]
NOTE:
Reserved
interrupt vector register
assignment register
Software watchdog
(IRQPAR) [p. 9-7]
(SWIVR) [p. 6-9]
Interrupt port
Reserved
Reserved
[15:8]
service register (SWSR)
Programming Model
Software watchdog
Autovector register
(AVR) [p. 9-5]
Reserved
[p. 6-9]
[7:0]
6-3