MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 138

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programming Model
5.4.4 Configuration/Status Register (CSR)
The configuration/status register (CSR) defines the debug configuration for the processor
and memory subsystem and contains status information from the breakpoint logic.
Table 5-8 describes CSR fields.
1
2
DRc[4–0]
5-10
CSR is write-only from the programming model. It can be read from and written to through the BDM port. CSR
is accessible in supervisor mode as debug control register 0x00 using the WDEBUG instruction and through
the BDM port using the
Bit 7 is reserved for Motorola use and must be written as a zero.
Reset
Reset
R/W
7
6–5
4–3
2–0
Field
Field MAP TRC EMU
Bits
R/W R/W R/W R/W
1
R
SZ
TT
TM
Name
31
15
0
30
14
0
BSTAT
Read/write
0 Write
1 Read
Size
00 Longword
01 Byte
10 Word
11 Reserved
Transfer type. See the TT definition in Table 5-4.
Transfer modifier. See the TM definition in Table 5-4.
0000
R
Figure 5-8. Configuration/Status Register (CSR)
29
13
0
RDMREG
Freescale Semiconductor, Inc.
28
12
For More Information On This Product,
Table 5-7. BAAR Field Descriptions
DDC
R/W
and
00
FOF TRG HALT BKPT
27
11
R
0
WDMREG
Go to: www.freescale.com
UHE
R/W
MCF5307 User’s Manual
26
10
R
0
0
commands.
25
R
0
9
BTB
R/W
00
24
R
0
8
Description
0x00
—
23
R
0
7
2
NPL
R/W
22
0
6
0001
HRL
R
IPI
—
—
21
5
SSM
R/W
20
0
4
19
—
—
—
3
BKD
—
—
18
2
—
—
—
—
—
—
17
1
R/W
IPW
16
0
0