MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 198

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PLL Operation
7.1.1 PLL:PCLK Ratios
The specifications for the clocks in the PLL module are summarized in Table 0-1.
7.2 PLL Operation
The following sections provide detailed information about the three PLL modes.
7.2.1 Reset/Initialization
The PLL receives RSTI as an input directly from the pin. Additionally, signals are
multiplexed with D[3:0]/FREQ[1:0]:DIVIDE[1:0] while RSTI is asserted. These signals
are sampled during reset and registered by the PLL on the negation of RSTI to provide
initialization information. FREQ[1:0] and DIVIDE[1:0] are used by the PLL to select the
CLKIN frequency range and set the CLKIN/PCLK ratio, respectively.
7.2.2 Normal Mode
PCLK is divided to create the system bus clock, BCLKO. At reset, the logic level of
DIVIDE[1:0]/D[1:0] determines the BCLKO divisor. The bus clock can be 1/2, 1/3, or 1/4
of the PCLK frequency.
7.2.3 Reduced-Power Mode
The PCLK can be turned off in a predictable manner to conserve system power. To allow
fast restart of the MCF5307 processor core, the PLL continues to operate at the frequency
configured at reset. PCLK is disabled using the CPU STOP instruction and resumes normal
operation on interrupt, as described in Section 7.2.4, “PLL Control Register (PLLCR).”
7-2
—
CLKIN
PCLK
PSTCLK
BCLKO
Symbol
BCLKO/PCLK ratio
PLL lock time
Input clock
Internal processor clock 33.34 MHz
Processor status clock
Output clock
Description
Freescale Semiconductor, Inc.
Table 0-1. PLL Clock Specifications
For More Information On This Product,
2.2 mS with CLKIN running at 45 MHz
16.67 MHz
33.34 MHz
16.67 MHz
Go to: www.freescale.com
MCF5307 User’s Manual
1/2
–
–
–
–
45 MHz
90 MHz (CLKIN x 2)
90 MHz (CLKIN x 2)
45 MHz
11.11 MHz
Frequency
1/3
–
30 MHz
8.24 MHz
–
1/4
22.5 MHz