MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 124

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Cache Operation Summary
Figure 4-11 shows the three possible cache line states and possible processor-initiated
transitions for memory configured as copyback. Transitions are labeled with a capital letter
indicating the previous state and a number indicating the specific case listed in Table 4-11.
Figure 4-12 shows the two possible states for a cache line in write-through mode.
Table 4-6 describes cache line transitions and the accesses that cause them.
4-26
WI3—CPU write miss
WI5—CINVA
WI6—CPUSHL & DPI
WI7—CPUSHL & DPI
CI5—CINVA
CI6—CPUSHL & DPI
CI7—CPUSHL & DPI
Figure 4-12. Cache Line State Diagram—Write-Through Mode
Figure 4-11. Cache Line State Diagram—Copyback Mode
CD5—CINVA
CD6—CPUSHL & DPI
Invalid
V = 0
Invalid
Freescale Semiconductor, Inc.
V = 0
CD2—CPU read hit
CD3—CPU write miss
CD4—CPU write hit
For More Information On This Product,
CI3—CPU
Go to: www.freescale.com
write miss
MCF5307 User’s Manual
WI1—CPU read miss
WV5—CINVA
WV6—CPUSHL & DPI
CI1—CPU read miss
CV5—CINVA
CV6—CPUSHL & DPI
CD7—CPUSHL
& DPI
Modified
M = 1
V = 1
CD1—CPU
read miss
CV3—CPU write miss
CV4—CPU write hit
V = 1
Valid
M = 0
V = 1
Valid
WV1—CPU read miss
WV2—CPU read hit
WV3—CPU write miss
WV4—CPU write hit
WV7—CPUSHL & DPI
CV1—CPU read miss
CV2—CPU read hit
CV7—CPUSHL & DPI