MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 411

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 18-8 defines the cycles for Figure 18-24.
Figure 18-25 shows a burst line access for an external master transfer with the chip select
set to no-wait states and with internal transfer-acknowledge assertion enabled.
C2–C3 The MCF5307 decodes the external master’s address and control signals to identify the proper chip select
Cycle
C10
C11
C1
C4
C5
C6
C7
C8
C9
The external master asserts HOLDREQ, signaling the MCF5307 to hold bus requests. BD should not be
asserted. The external master drives address, TS, R/W, TT[1:0], TM[2:0], TIP, and SIZ[1:0] as MCF5307
inputs.
and byte enable assertion. The external master negates TS in C2.
On the falling edge of BCLKO, the MCF5307 asserts the appropriate chip select for the external master
access along with the appropriate byte enables.
On the rising edge of BCLKO, data is driven onto the bus by the device selected by CS. On the rising edge,
the MCF5307 asserts TA to indicate the cycle is complete.
TA negates on the rising edge of BCLKO. On the falling edge, the MCF5307 negates the chip select and
byte enables and the next cycle can begin.
The external master negates TIP on the rising edge of BCLKO.
The external device retains bus mastership and drives the address bus, TS, R/W, TT[1:0], TM[2:0], TIP, and
SIZ[1:0] as inputs to the MCF5307.
The MCF5307 decodes the external master’s address and control signals to identify the proper chip select
and byte enable assertion. The external master negates TS. The MCF5307 asserts BR on the rising edge of
BCLKO, signalling that it wants to arbitrate for the bus when the current cycle completes.
The MCF5307 continues to decode the external device’s address and control signals to identify the proper
chip select and byte enable assertion.
On the falling edge of BCLKO, the MCF5307 asserts the appropriate chip select for the external master
access along with the appropriate byte enables.
Table 18-8. Cycles for Basic No-Wait-State External Master Access
Bus timing diagrams for external master transfers are not valid
for on-chip internal four-channel DMA accesses on the
MCF5307.
Timing diagrams describe transactions in general terms of bus
cycles (Cn) rather than the states (Sn) used in the bus diagrams.
Freescale Semiconductor, Inc.
For More Information On This Product,
Chapter 18. Bus Operation
Go to: www.freescale.com
NOTE:
Definition
General Operation of External Master Transfers
18-23