MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 469

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Glossary of Terms and Abbreviations
The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this
book.
B
A
C
Architecture. A detailed specification of requirements for a processor or
Autovector. A method of determining the starting address of the service
Branch prediction.The process of guessing whether a branch will be taken.
Branch resolution.The determination of whether a branch is taken or not
Burst. A multiple-beat data transfer.
Cache. High-speed memory containing recently accessed data and/or
Cache coherency. An attribute wherein an accurate and common view of
computer system. It does not specify details of how the processor or
computer system must be implemented; instead it provides a
template for a family of compatible implementations.
routine by fetching the value from a lookup table internal to the
processor instead of requesting the value from the system.
Such predictions can be correct or incorrect; the term ‘predicted’ as
it is used here does not imply that the prediction is correct
(successful).
taken. A branch is said to be resolved when the processor can
determine which instruction path to take. If the branch is resolved as
predicted, the instructions following the predicted branch that may
have been speculatively executed can complete (see completion). If
the branch is not resolved as predicted, instructions on the
mispredicted path, and any results of speculative execution, are
purged from the pipeline and fetching continues from the
nonpredicted path.
instructions (subset of main memory).
memory is provided to all devices that share the same memory
system. Caches are coherent if a processor performing a read from
Freescale Semiconductor, Inc.
For More Information On This Product,
Glossary of Terms and Abbreviations
Go to: www.freescale.com
Glossary-11