MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 171

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The CSR provides capabilities to display operands based on reference type (read, write, or
both). Additionally, for certain change-of-flow branch instructions, another CSR field
provides the capability to display {0x2, 0x3, 0x4} bytes of the target instruction address.
For both situations, an optional PST value {0x8, 0x9, 0xB} provides the marker identifying
the size and presence of valid data on the DDATA output.
5.8.1 User Instruction Set
Table 5-22 shows the PST/DDATA specification for user-mode instructions. Rn represents
any {Dn, An} register. In this definition, the ‘y’ suffix generally denotes the source and ‘x’
denotes the destination operand. For a given instruction, the optional operand data is
displayed only for those effective addresses referencing memory. The ‘DD’ nomenclature
refers to the DDATA outputs.
add.l
add.l
addi.l
addq.l
addx.l
and.l
and.l
andi.l
asl.l
asr.l
bcc.{b,w}
bchg
bchg
bclr
bclr
bra.{b,w}
bset
bset
bsr.{b,w}
btst
btst
clr.b
clr.l
clr.w
Instruction
Table 5-22. PST/DDATA Specification for User-Mode Instructions
<ea>y,Rx
Dy,<ea>x
#imm,Dx
#imm,<ea>x
Dy,Dx
<ea>y,Dx
Dy,<ea>x
#imm,Dx
{Dy,#imm},Dx
{Dy,#imm},Dx
#imm,<ea>x
Dy,<ea>x
#imm,<ea>x
Dy,<ea>x
#imm,<ea>x
Dy,<ea>x
#imm,<ea>x
Dy,<ea>x
<ea>x
<ea>x
<ea>x
Operand Syntax
Freescale Semiconductor, Inc.
For More Information On This Product,
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1
PST = 0x1
if taken, then PST = 0x5, else PST = 0x1
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x5
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x5, {PST = 0xB, DD = destination operand}
PST = 0x1, {PST = 0x8, DD = source operand}
PST = 0x1, {PST = 0x8, DD = source operand}
PST = 0x1, {PST = 0x8, DD = destination operand}
PST = 0x1, {PST = 0xB, DD = destination operand}
PST = 0x1, {PST = 0x9, DD = destination operand}
Chapter 5. Debug Support
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PST/DDATA
Processor Status, DDATA Definition
5-43