MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 384

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor, Inc.
Debug and Test Signals
17.13 Debug and Test Signals
The signals in this section interface with external I/O to provide processor status signals.
17.13.1 Test Mode (MTMOD[3:0])
The test mode signals choose between multiplexed debug module and JTAG signals. If
MTMOD0 is low, the part is in normal and background debug mode (BDM); if it is high,
it is in normal and JTAG mode. All other MTMOD values are reserved; MTMOD[3:1]
should be tied to ground and MTMOD[3:0] should not be changed while RSTI is negated.
17.13.2 High Impedance (HIZ)
The assertion of HIZ forces all output drivers to high-impedance state. The timing on HIZ
is independent of the clock. Note that HIZ does not override the JTAG operation;
TDO/DSO can be forced to high impedance by asserting TRST.
17.13.3 Processor Clock Output (PSTCLK)
The internal PLL generates this output signal, and is the processor clock output that is used
as the timing reference for the debug bus timing (DDATA[3:0] and PST[3:0]). PSTCLK is
at the same frequency as the core processor and cache memory. The frequency is 2x the
CLKIN.
17.13.4 Debug Data (DDATA[3:0])
The debug data signals (DDATA[3:0]) display captured processor data and breakpoint
status. See Chapter 5, “Debug Support,” for additional information on this bus.
17.13.5 Processor Status (PST[3:0])
The processor status pins indicate the MCF5307 processor status. During debug mode, the
timing is synchronous with the processor clock (PSTCLK) and the status is not related to
the current bus transfer. Table 2-11 shows the encodings of these signals.
17-20
MCF5307 User’s Manual
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