MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 191

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.2.10 Bus Arbitration Control
This section describes the bus arbitration register and the four arbitration schemes.
6.2.10.1 Default Bus Master Park Register (MPARK)
The MPARK, shown in Figure 6-9, determines the default bus master arbitration between
internal transfers (core and DMA module) and between internal and external transfers to
internal resources. This arbitration is needed because external masters can access internal
registers within the MCF5307 peripherals.
Table 6-6 describes MPARK bits.
Address
Bits
7–6
5
4
Reset
Field
R/W
EARBCTRL External bus arbitration control. Enables internal register memory space to external bus
IARBCTRL
Name
PARK
7
PARK
Figure 6-9. Default Bus Master Register (MPARK)
Park. Indicates the arbitration priority of internal transfers among MCF5307 resources.
00 Round-robin between DMA and ColdFire core
01 Park on master ColdFire core
10 Park on master DMA module
11 Park on current master
Use of this field is described in detail in Section 6.2.10.1.1, “Arbitration for Internally
Generated Transfers (MPARK[PARK]).”
Internal bus arbitration control. Controls external device access to the MCF5307 internal bus.
0 Arbitration disabled (single-master system)
1 Arbitration enabled. IARBCTRL must be set if external masters are using internal
Use of this bit depends on whether the system has single or multiple masters, as follows:
arbitration. Internal registers are those accessed at offsets to the MBAR. These include the
SIM, DMA, chip selects, timers, UARTs, I
not include the MBAR; only the core can access the MBAR.
0 Arbitration disabled
1 Arbitration enabled
The use of this field is described in detail in Section 6.2.10.1.2, “Arbitration between Internal
and External Masters for Accessing Internal Resources.”
• In a single-master system, IARBCTRL should stay cleared, disabling internal arbitration
• In multiple master systems that expect to use internal resources like the DRAM controller
resources like the DRAM controller or chip selects.
by external masters. In this scenario, MPARK[PARK] applies only to priority of internal
masters over one another. Note that the internal DMA (master 3) has priority over the
ColdFire core (master 2), if internal DMA bandwidth is at its maximum (BWC = 000).
or chip selects, internal arbitration should be enabled. The external master defaults to the
highest priority internal master anytime BG is negated.
6
Freescale Semiconductor, Inc.
Table 6-6. MPARK Field Descriptions
For More Information On This Product,
IARBCTRL EARBCTRL SHOWDATA
Chapter 6. SIM Overview
5
Go to: www.freescale.com
4
MBAR + 0x0C
0000_0000
R/W
Description
2
C, and parallel port registers. These registers do
3
2
—
Programming Model
BCR24BIT
0
6-11