MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 272
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MCF5307AI90B
Manufacturer Part Number
MCF5307AI90B
Description
IC MPU 32BIT COLDF 90MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307AI90B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
90MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Maximum Clock Frequency
90 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
90MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
FQFP
Program Memory Size
8KB
Cpu Speed
90MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5307AI90B
Manufacturer:
FREESCAL
Quantity:
153
Company:
Part Number:
MCF5307AI90B
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCF5307AI90B
Manufacturer:
FREESCALE
Quantity:
20 000
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SDRAM Example
11.5.5 Mode Register Initialization
When DACR[IMRS] is set, a bus cycle initializes the mode register. If the mode register
setting is read on A[10:0] of the SDRAM on the first bus cycle, the bit settings on the
corresponding MCF5307 address pins must be determined while being aware of masking
requirements.
Table 11-37 lists the desired initialization setting:
Next, this information is mapped to an address to determine the hexadecimal value.
Although A[31:20] corresponds to the address programmed in DACR0, according to how
DACR0 and DMR0 are initialized, bit 19 must be set to hit in the SDRAM. Thus, before
the mode register bit is set, DMR0[19] must be set to enable masking.
11-38
Setting
Setting
(hex)
(hex)
Field
Field
31
15
X
0
Figure 11-29. Mode Register Mapping to MCF5307 A[31:0]
30
14
X
0
MCF5307 Pins
0
0
29
13
X
0
A20
A19
A18
A17
A10
A11
A12
A13
A14
A15
A9
Table 11-37. Mode Register Initialization
Freescale Semiconductor, Inc.
28
12
X
0
For More Information On This Product,
27
11
X
1
SDRAM Pins
Go to: www.freescale.com
MCF5307 User’s Manual
26
10
X
0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
8
25
X
0
9
24
X
X
8
Mode Register Initialization
Reserved
Opmode
Opmode
CASL
CASL
CASL
23
WB
X
X
BT
7
BL
BL
BL
22
X
X
6
0
0
21
X
X
5
20
X
X
4
X
0
0
0
0
0
1
0
0
0
0
19
X
0
3
18
X
0
2
0
0
17
X
0
1
16
X
V
X
0
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