MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 99

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 4
Local Memory
This chapter describes the MCF5307 implementation of the ColdFire Version 3 local
memory specification. It consists of two major sections.
4.1 Interactions between Local Memory Modules
Depending on configuration information, instruction fetches and data read accesses may be
sent simultaneously to the RAM and cache controllers. This approach is required because
both controllers are memory-mapped devices and the hit/miss determination is made
concurrently with the read data access. Power dissipation can be minimized by configuring
the RAMBARs to mask unused address spaces whenever possible.
If the access address is mapped into the region defined by the RAM (and this region is not
masked), the RAM provides the data back to the processor, and the cache data is discarded.
Accesses from the RAM module are never cached. The complete definition of the
processor’s local bus priority scheme for read references is as follows:
)
For data write references, the memory mapping into the local memories is resolved before
the appropriate destination memory is accessed. Accordingly, only the targeted local
memory is accessed for data write transfers.
4.2 SRAM Overview
The 4-Kbyte on-chip SRAM module is connected to the internal bus and provides pipelined,
single-cycle access to memory mapped to the module. Memory can be mapped to any
• Section 4.2, “SRAM Overview,” describes the MCF5307 on-chip static RAM
• Section 4.7, “Cache Overview,” describes the MCF5307 cache implementation,
(SRAM) implementation. It covers general operations, configuration, and
initialization. It also provides information and examples showing how to minimize
power consumption when using the SRAM.
including organization, configuration, and coherency. It describes cache operations
and how the cache interfaces with other memory structures.
if (RAM “hits”
RAM supplies data to the processor
else if (cache “hits”)
else system memory reference to access data
Freescale Semiconductor, Inc.
For More Information On This Product,
cache supplies data to the processor
Chapter 4. Local Memory
Go to: www.freescale.com
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