MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 421

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 18-11. Three-Wire Bus Arbitration Protocol Transition Conditions (Continued)
1
The bus arbitration state diagram can be used for the MCF5307 three-wire bus arbitration
protocol to approximate the high-level behavior of the MCF5307. It is assumed that all TS
or AS signals in a system are tied together and each bus device’s BD and BR signals are
connected individually to the external arbiter. The external arbiter must ensure that any
external masters will have released the bus after the next rising edge of before asserting BG
to the MCF5307. The MCF5307 does not monitor external bus master operation regarding
bus arbitration.
18.10 Reset Operation
The MCF5307 supports two types of reset. Asserting RSTI resets the entire MCF5307. A
software watchdog reset resets everything but the internal PLL module.
External
Current
Both normal terminations and terminations due to bus errors generate an end of cycle. Bus cycles resulting from
a burst-inhibited transfer are considered part of that original transfer.
Explicit
master
master
State
Condition
Label
C1
C2
C3
C4
C5
D1
D2
D3
D4
The MCF5307 can start a transfer on the rising edge of the
cycle after BG is asserted. The external arbiter should not assert
BG to the MCF5307 until the previous external master stops
driving the bus or the part may be damaged.
Negated
Negated
Negated
Negated
Negated
Negated
Negated
Negated
Negated
RSTI
Freescale Semiconductor, Inc.
For More Information On This Product,
Watchdog
Software
Negated
Negated
Negated
Negated
Negated
Negated
Negated
Negated
Negated
Chapter 18. Bus Operation
Reset
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NOTE:
Negated
Asserted
Asserted
Asserted
Asserted
Negated
Negated
Negated
Negated
BG
1
Asserted
Request
Negated
Bus
—
—
—
—
—
—
—
Progress
Transfer
Negated
Yes
Yes
—
—
—
—
—
—
in
Negated
Cycle
End of
Yes
—
—
—
—
—
—
—
Reset Operation
1
Next State
External
External
External
Explicit
Explicit
Explicit
Explicit
Implicit
Explicit
master
master
master
master
master
master
master
master
master
device
device
device
18-33