HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet
HD64F3026X25
Specifications of HD64F3026X25
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HD64F3026X25 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8/3024 Group, H8/3024F-ZTAT 16 H8/3026F-ZTAT Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series H8/3024 H8/3026 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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The H8/3024 Group is a high-performance single-chip microcomputer that integrates peripheral functions necessary for system configuration with an H8/300H CPU featuring a 32-bit internal architecture as its core. The on-chip peripheral functions include ROM, RAM, 16-bit timers, 8-bit timers, a ...
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User's Manuals on the H8/3024: Manual Title H8/3024 Hardware Manual H8/300H Series Programming Manual Users manuals for development tools: Manual Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual H8S, H8/300 Series Simulator/Debugger User’s Manual High-Performance Embedded ...
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Comparison of H8/3024 Group Product Specifications There are four members of the H8/3024 Group: the H8/3024F-ZTAT and H8/3026F-ZTAT (all with on-chip flash memory), and the H8/3024 mask ROM version and H8/3026 mask ROM version. The specifications of these products are ...
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Rev. 2.00 Sep 20, 2005 page vi of xxxviii ...
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Main Revisions for This Edition Item Page All 7.12.2 Register 203, 204 Description amended Descriptions Table 7.23 Port B Pin Functions (Modes Table 7.24 Port B 205, 206 PB Pin Functions (Modes 6 and 7) 18.5.1 Boot ...
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Rev. 2.00 Sep 20, 2005 page viii of xxxviii ...
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Section 1 Overview ............................................................................................................. 1.1 Overview........................................................................................................................... 1.2 Block Diagram.................................................................................................................. 1.3 Pin Description ................................................................................................................. 1.3.1 Pin Arrangement.................................................................................................. 1.3.2 Pin Functions ....................................................................................................... 10 1.3.3 Pin Assignments in Each Mode ........................................................................... 15 1.4 Caution on Crystal Resonator Connection........................................................................ 18 Section 2 CPU ...................................................................................................................... ...
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Reset State ........................................................................................................... 53 2.8.7 Power-Down State ............................................................................................... 53 2.9 Basic Operational Timing ................................................................................................. 53 2.9.1 Overview.............................................................................................................. 53 2.9.2 On-Chip Memory Access Timing........................................................................ 54 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 55 2.9.4 Access to External Address Space....................................................................... 56 ...
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Section 5 Interrupt Controller 5.1 Overview........................................................................................................................... 83 5.1.1 Features................................................................................................................ 83 5.1.2 Block Diagram..................................................................................................... 84 5.1.3 Pin Configuration ................................................................................................ 85 5.1.4 Register Configuration......................................................................................... 85 5.2 Register Descriptions........................................................................................................ 85 5.2.1 System Control Register (SYSCR)...................................................................... 85 5.2.2 Interrupt Priority Registers A and B ...
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Bus Specifications ............................................................................................... 127 6.3.3 Memory Interfaces............................................................................................... 128 6.3.4 Chip Select Signals .............................................................................................. 129 6.3.5 Address Output Method....................................................................................... 130 6.4 Basic Bus Interface ........................................................................................................... 131 6.4.1 Overview.............................................................................................................. 131 6.4.2 Data Size and Data Alignment............................................................................. 131 6.4.3 Valid Strobes ....................................................................................................... ...
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Overview.............................................................................................................. 175 7.8.2 Register Description ............................................................................................ 176 7.9 Port 8................................................................................................................................. 176 7.9.1 Overview.............................................................................................................. 176 7.9.2 Register Descriptions........................................................................................... 177 7.10 Port 9................................................................................................................................. 182 7.10.1 Overview.............................................................................................................. 182 7.10.2 Register Descriptions........................................................................................... 183 7.11 Port A................................................................................................................................ 187 7.11.1 Overview.............................................................................................................. 187 7.11.2 Register Descriptions........................................................................................... ...
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Phase Counting Mode.......................................................................................... 252 8.4.6 16-Bit Timer Output Timing................................................................................ 254 8.5 Interrupts........................................................................................................................... 255 8.5.1 Setting of Status Flags ......................................................................................... 255 8.5.2 Timing of Clearing of Status Flags...................................................................... 257 8.5.3 Interrupt Sources.................................................................................................. 258 8.6 Usage Notes ...................................................................................................................... 259 Section 9 ...
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Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode (Cascaded Connection)........................................................................................ 306 9.7.8 Contention between Compare Matches A and B ................................................. 307 9.7.9 8TCNT Operation and Internal Clock Source Switchover .................................. 307 Section 10 Programmable Timing Pattern ...
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Reset Control/Status Register (RSTCSR)............................................................ 342 11.2.4 Notes on Register Access .................................................................................... 344 11.3 Operation .......................................................................................................................... 346 11.3.1 Watchdog Timer Operation ................................................................................. 346 11.3.2 Interval Timer Operation ..................................................................................... 347 11.3.3 Timing of Setting of Overflow Flag (OVF)......................................................... 347 11.3.4 Timing ...
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Smart Card Mode Register (SCMR).................................................................... 418 13.2.2 Serial Status Register (SSR) ................................................................................ 420 13.2.3 Serial Mode Register (SMR) ............................................................................... 421 13.2.4 Serial Control Register (SCR) ............................................................................. 422 13.3 Operation .......................................................................................................................... 423 13.3.1 Overview.............................................................................................................. 423 13.3.2 Pin Connections................................................................................................... 423 13.3.3 ...
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D/A Standby Control Register (DASTCR).......................................................... 468 15.3 Operation .......................................................................................................................... 468 15.4 D/A Output Control .......................................................................................................... 470 Section 16 RAM .................................................................................................................. 471 16.1 Overview........................................................................................................................... 471 16.1.1 Block Diagram..................................................................................................... 472 16.1.2 Register Configuration......................................................................................... 472 16.2 System Control Register (SYSCR) ................................................................................... 473 ...
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NMI Input Disabling Conditions ...................................................................................... 518 17.10 Flash Memory PROM Mode ............................................................................................ 519 17.10.1 Socket Adapters and Memory Map ..................................................................... 519 17.10.2 Notes on Use of PROM Mode............................................................................. 520 17.11 Flash Memory Programming and Erasing Precautions..................................................... 520 17.12 Mask ...
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Socket Adapters and Memory Map ..................................................................... 571 18.10.2 Notes on Use of PROM Mode............................................................................. 572 18.11 Flash Memory Programming and Erasing Precautions..................................................... 573 18.12 Notes when Converting the F-ZTAT Application Software to the Mask ROM Versions 579 Section 19 ...
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System Clock Output Disabling Function ........................................................................ 605 Section 21 Electrical Characteristics 21.1 Electrical Characteristics of H8/3024 Mask ROM Version and H8/3026 Mask ROM Version .................................................................................... 607 21.1.1 Absolute Maximum Ratings ................................................................................ 607 21.1.2 DC Characteristics ............................................................................................... 608 21.1.3 AC ...
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C.6 Port 6 Block Diagrams...................................................................................................... 759 C.7 Port 7 Block Diagrams...................................................................................................... 764 C.8 Port 8 Block Diagrams...................................................................................................... 765 C.9 Port 9 Block Diagrams...................................................................................................... 769 C.10 Port A Block Diagrams..................................................................................................... 775 C.11 Port B Block Diagrams ..................................................................................................... 778 Appendix D Pin ...
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Section 1 Overview Figure 1.1 Block Diagram..................................................................................................... Figure 1.2 Pin Arrangement of H8/3024F-ZTAT, H8/3026F-ZTAT, H8/3024 Mask ROM Version, and H8/3026 Mask ROM Version (FP-100B or TFP-100B Package, Top View)...................................................... Figure 1.3 Pin Arrangement of H8/3024F-ZTAT, H8/3026F-ZTAT, H8/3024 Mask ROM Version, ...
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Figure 4.3 Reset Sequence (Modes 2 and 4)......................................................................... 76 Figure 4.4 Reset Sequence (Mode 6) .................................................................................... 77 Figure 4.5 Interrupt Sources and Number of Interrupts ........................................................ 78 Figure 4.6 Stack after Completion of Exception Handling ................................................... 79 Figure 4.7 Operation ...
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Figure 6.15 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3) (Word Access) ..................................................................................................... 141 Figure 6.16 Example of Wait State Insertion Timing ............................................................. 142 Figure 6.17 Example of Idle Cycle Operation (ICIS1 = 1) ..................................................... 143 Figure 6.18 Example ...
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Figure 8.17 Setup Procedure for Waveform Output by Compare Match (Example) .............. 242 Figure 8.18 0 and 1 Output (TOA = 1, TOB = 0) ................................................................... 243 Figure 8.19 Toggle Output (TOA = 1, TOB = 0).................................................................... 243 Figure 8.20 ...
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Figure 9.12 Timing of Clear by Input Capture........................................................................ 291 Figure 9.13 Timing of Input Capture Input Signal.................................................................. 292 Figure 9.14 CMF Flag Setting Timing when Compare Match Occurs ................................... 292 Figure 9.15 CMFB Flag Setting Timing when Input Capture Occurs ...
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Figure 12.3 Phase Relationship between Output Clock and Serial Data (Asynchronous Mode) ......................................................................................... 385 Figure 12.4 Sample Flowchart for SCI Initialization .............................................................. 386 Figure 12.5 Sample Flowchart for Transmitting Serial Data .................................................. 387 Figure 12.6 Example of SCI Transmit Operation ...
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Figure 13.12 Retransmission in SCI Receive Mode ................................................................. 439 Figure 13.13 Retransmission in SCI Transmit Mode................................................................ 440 Section 14 A/D Converter Figure 14.1 A/D Converter Block Diagram ............................................................................ 442 Figure 14.2 A/D Data Register Access Operation (Reading H'AA40) ................................... 450 ...
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Figure 17.16 Power-On/Off Timing (Boot Mode).................................................................... 523 Figure 17.17 Power-On/Off Timing (User Program Mode) ..................................................... 524 Figure 17.18 Mode Transition Timing (Example: Boot Mode Figure 17.19 ROM Block Diagram (H8/3026 Mask ROM Version)........................................ 526 Figure 17.20 Mask ROM Addresses and ...
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Figure 20.3 Starting and Stopping of System Clock Output ................................................... 605 Section 21 Electrical Characteristics Figure 21.1 Darlington Pair Drive Circuit (Example)............................................................. 611 Figure 21.2 Sample LED Circuit ............................................................................................ 611 Figure 21.3 Output Load Circuit............................................................................................. 615 Figure 21.4 Darlington Pair ...
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Figure C.9 (b) Port 9 Block Diagram (Pin P9 Figure C.9 (c) Port 9 Block Diagram (Pin P9 Figure C.9 (d) Port 9 Block Diagram (Pin P9 Figure C.9 (e) Port 9 Block Diagram (Pin P9 Figure C.9 (f) Port ...
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Section 1 Overview Table 1.1 Features................................................................................................................ Table 1.2 Comparison of H8/3024 Group Pin Arrangements.............................................. Table 1.3 Pin Functions ....................................................................................................... 10 Table 1.4 Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A) .................. 15 Section 2 CPU Table 2.1 Instruction Classification ...
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Section 6 Bus Controller Table 6.1 Bus Controller Pins.............................................................................................. 111 Table 6.2 Bus Controller Registers...................................................................................... 112 Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ..................................... 128 Table 6.4 Data Buses Used and Valid Strobes..................................................................... 133 Table 6.5 Pin ...
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Table 8.7 (b) 16-bit timer Operating Modes (Channel 1).......................................................... 269 Table 8.7 (c) 16-bit timer Operating Modes (Channel 2).......................................................... 270 Section 9 8-Bit Timers Table 9.1 8-Bit Timer Pins .................................................................................................. 274 Table 9.2 8-Bit Timer Registers .......................................................................................... 275 Table 9.3 ...
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Table 13.3 Smart Card Interface Register Settings................................................................ 426 Table 13.4 n-Values of CKS1 and CKS0 Settings................................................................. 428 Table 13.5 Bit Rates (bits/s) for Various BRR Settings (When .................................. 428 Table 13.6 BRR Settings for Typical Bit Rates ...
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Table 18.6 On-Board Programming Mode Settings .............................................................. 547 Table 18.7 System Clock Frequencies for which Automatic Adjustment of H8/3024F-ZTAT Version Bit Rate is Possible................................................ 550 Table 18.8 Hardware Protection ............................................................................................ 565 Table 18.9 Software Protection ............................................................................................. 566 Table 18.10 H8/3024F-ZTAT ...
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Appendix A Instruction Set Table A.1 Instruction Set...................................................................................................... 641 Table A.2 Operation Code Map (1)...................................................................................... 654 Table A.2 Operation Code Map (2)...................................................................................... 655 Table A.2 Operation Code Map (3)...................................................................................... 656 Table A.3 Number of States per Cycle ................................................................................. 658 Table ...
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Overview The H8/3024 Group is a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Renesas Technology architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general ...
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Section 1 Overview Table 1.1 Features Feature Description CPU Upward-compatible with the H8/300 CPU at the object-code level General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers plus eight 16-bit registers eight 32-bit registers) High-speed ...
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Feature Description Bus controller Address space can be partitioned into eight areas, with independent bus specifications in each area Chip select output available for areas 8-bit access or 16-bit access selectable for each area Two-state or three-state ...
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Section 1 Overview Feature Description A/D converter Resolution: 10 bits Eight channels, with selection of single or scan mode Variable analog conversion voltage range Sample-and-hold function A/D conversion can be started by an external trigger or 8-bit timer compare- match ...
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Feature Description Product lineup Product Type H8/3024F-ZTAT H8/3026F-ZTAT H8/3024 mask ROM version H8/3026 mask ROM version Model 3.3 V operation HD64F3024F HD64F3024TE HD64F3024FP 3.3 V operation HD64F3026F HD64F3026TE HD64F3026FP 3.3 V operation HD6433024F HD6433024TE HD6433024FP 3.3 V operation HD6433026F HD6433026TE ...
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Section 1 Overview 1.2 Block Diagram Figure 1.1 shows an internal block diagram EXTAL XTAL STBY RES RESO/FWE * NMI /P6 7 LWR/P6 6 HWR/P6 5 RD/P6 4 AS/P6 3 BACK/P6 2 BREQ/P6 1 ...
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Pin Description 1.3.1 Pin Arrangement The pin arrangement of the H8/3024 Group is shown in figures 1.2 to 1.5. Differences in the H8/3024 Group pin arrangements are shown in table 1.2. Except for the differences shown in table 1.2, ...
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Section 1 Overview REF ...
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/AN / /AN / ...
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Section 1 Overview 1.3.2 Pin Functions Table 1.3 summarizes the pin functions. Table 1.3 Pin Functions FP-100B Type Symbol TFP-100B FP-100A I/O Power 11, 22, SS 44, 57, 65, 92 Clock XTAL 67 EXTAL ...
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Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O System control FWE Interrupts NMI 64 to ...
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Section 1 Overview FP-100B Type Symbol TFP-100B FP-100A I/O Bus control 16-bit TCLKD to timer TCLKA TIOCA to 99, 97 99, 97 Input/ 2 TIOCA 0 TIOCB to 100, 98, ...
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Pin No. FP-100B Type Symbol TFP-100B FP-100A I converter Analog power supply Analog power supply V 77 REF I/O ports ...
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Section 1 Overview FP-100B Type Symbol TFP-100B FP-100A I/O I/O ports 100 Rev. 2.00 Sep 20, 2005 page 14 of 800 REJ09B0260-0200 Pin ...
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Pin Assignments in Each Mode Table 1.4 lists the pin assignments in each mode. Table 1.4 Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A) Pin No. FP-100B TFP-100B FP-100A Mode ...
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Section 1 Overview Pin No. FP-100B TFP-100B FP-100A Mode ...
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Pin No. FP-100B TFP-100B FP-100A Mode ...
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Section 1 Overview Pin No. FP-100B TFP-100B FP-100A Mode ...
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Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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Section 2 CPU 16 16-bit register-register multiply: 32 ÷ 16-bit register-register divide: Two CPU operating modes Normal mode Advanced mode Low-power mode Transition to power-down state by SLEEP instruction 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, ...
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Address Space Figure 2.2 shows a simple memory map for the H8/3024 Group. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in advanced mode. For ...
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Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) 15 ER0 ER1 ER2 ER3 ER4 ER5 ...
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General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, ...
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Section 2 CPU SP (ER7) 2.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR). Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will ...
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Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3—Negative Flag (N): Stores the value of the most significant bit of data, regarded as the sign bit. Bit ...
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Section 2 CPU 2.5 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … ...
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General Data Type Register Data Format Word data Rn 15 Word data En MSB 31 Longword data ERn MSB Legend: ERn: General register En: General register E Rn: General register R MSB: Most significant bit LSB: Least significant bit Figure ...
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Section 2 CPU Data Type 1-bit data Byte data Word data Longword data When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size. Rev. 2.00 Sep 20, ...
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Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 64 types of instructions, which are classified in table 2.1. Table 2.1 Instruction Classification Function Instruction MOV, PUSH * Data transfer Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ...
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Section 2 CPU 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes Function Instruction Data MOV BWL transfer POP, PUSH — MOVFPE, — MOVTPE Arithmetic ADD, CMP BWL ...
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Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation General register (destination General register (source ...
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Section 2 CPU Table 2.3 Data Transfer Instructions Instruction Size * Function MOV B/W/L (EAs) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) Cannot ...
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Table 2.4 Arithmetic Operation Instructions Instruction Size * Function ADD,SUB B/W/L Rd ± Rs Performs addition or subtraction on data in two general registers immediate data and data in a general register. (Immediate byte data cannot be subtracted ...
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Section 2 CPU Instruction Size * Function DIVXU B/W Rd ÷ Rs Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits and 16-bit ...
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Table 2.5 Logic Operation Instructions Instruction Size * Function AND B/W Performs a logical AND operation on a general register and another general register or immediate data. OR B/W Performs a logical OR operation on a ...
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Section 2 CPU Table 2.7 Bit Manipulation Instructions Instruction Size * Function BSET B 1 (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data ...
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Instruction Size * Function BOR B C (<bit-No.> of <EAd>) ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit ...
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Section 2 CPU Table 2.8 Branching Instructions Instruction Size Function Bcc — Branches to a specified address if address specified condition is met. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS Bcc (BHS) BCS (BLO) ...
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Table 2.9 System Control Instructions Instruction Size * Function TRAPA — Starts trap-instruction exception handling RTE — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state LDC B/W (EAs) Moves the source operand contents to ...
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Section 2 CPU Table 2.10 Block Transfer Instruction Instruction Size Function EEPMOV.B — if R4L repeat until else next; EEPMOV.W — then repeat until else next; Block transfer instruction. This instruction transfers the number of data bytes ...
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Operation field only Operation field and register fields op Operation field, register fields, and effective address extension op Operation field, effective address extension, and condition field op cc 2.6.5 Notes on Use of Bit Manipulation Instructions The BSET, BCLR, BNOT, ...
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Section 2 CPU Before Execution of BCLR Instruction Input/output Input Input DDR 0 0 Execution of BCLR Instruction BCLR #0, P4DDR ; Execute BCLR instruction on DDR After Execution of BCLR Instruction ...
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Addressing Modes and Effective Address Calculation 2.7.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct ...
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Section 2 CPU 4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn: Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory ...
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Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign- extended to 24 bits and added to the 24-bit PC contents ...
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Section 2 CPU Table 2.13 Effective Address Calculation Rev. 2.00 Sep 20, 2005 page 46 of 800 REJ09B0260-0200 ...
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Section 2 CPU Rev. 2.00 Sep 20, 2005 page 47 of 800 REJ09B0260-0200 ...
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Section 2 CPU Rev. 2.00 Sep 20, 2005 page 48 of 800 REJ09B0260-0200 ...
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Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2.11 ...
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Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception ...
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End of bus release Bus-released state End of exception handling Exception-handling state RES = "High" *1 Reset state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. From any ...
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Section 2 CPU is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then the CPU fetches a start address from the exception vector table and execution branches ...
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Reset State When the input goes low all current processing stops and the CPU enters the reset state. The bit in the condition code register is set reset. All interrupts are ...
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Section 2 CPU 2.9.2 On-Chip Memory Access Timing On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and word access. Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the ...
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On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus bits wide, depending on the internal I/O register being accessed. Figure 2.17 shows the on-chip supporting module access ...
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Section 2 CPU 2.9.4 Access to External Address Space The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings determine whether each area is accessed via an 8-bit or 16-bit data bus, and whether it ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8/3024 Group has seven operating modes (modes that are selected by the mode pins ( indicated in table 3.1. The input ...
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Section 3 MCU Operating Modes Mode externally expanded mode that enables access to external memory and peripheral devices and also enables access to the on-chip ROM. Mode 5 supports a maximum address space of 16 Mbytes. Modes ...
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Mode Control Register (MDCR) MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3024 Group. Bit 7 — Initial value 1 Read/Write — Note: * Determined by pins Bits 7 ...
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Section 3 MCU Operating Modes 3.3 System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3024 Group. Bit 7 SSBY STS2 Initial value 0 Read/Write R/W R/W Standby timer select These ...
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Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by ...
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Section 3 MCU Operating Modes Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and bus control signals ( the high-impedance state in software standby mode. Bit 1 SSOE Description ...
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Mode 3 Ports 1, 2, and 5 and part of port A function as address pins A maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas ...
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Section 3 MCU Operating Modes 3.5 Pin Functions in Each Operating Mode The pin functions of ports and port A vary depending on the operating mode. Table 3.3 indicates their functions in each operating mode. Table 3.3 ...
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Memory Map in Each Operating Mode Figures 3.1 to 3.2 show memory maps of the H8/3024 Group. In the expanded modes, the address space is divided into eight areas. The initial bus mode differs between modes 1 and 2, ...
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Section 3 MCU Operating Modes Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'EE000 Internal I/O ...
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Mode 5 (16-Mbyte expanded mode with on-chip ROM enabled) H'000000 Vector area H'0000FF On-chip ROM H'007FFF H'01FFFF H'020000 Area 0 H'1FFFFF H'200000 Area 1 H'3FFFFF H'400000 Area 2 H'5FFFFF H'600000 External address Area 3 space H'7FFFFF H'800000 Area 4 H'9FFFFF ...
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Section 3 MCU Operating Modes Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'EE000 Internal I/O ...
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Mode 5 (16-Mbyte expanded mode with on-chip ROM enabled) H'000000 Vector area H'0000FF On-chip ROM (flash memory) H'007FFF H'03FFFF H'040000 Area 0 H'1FFFFF H'200000 Area 1 H'3FFFFF H'400000 Area 2 H'5FFFFF H'600000 External address Area 3 space H'7FFFFF H'800000 Area ...
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Section 3 MCU Operating Modes Rev. 2.00 Sep 20, 2005 page 70 of 800 REJ09B0260-0200 ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or ...
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Section 4 Exception Handling 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. • Reset Exception • ...
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Table 4.2 Exception Vector Table Exception Source Reset Reserved for system use External interrupt (NMI) Trap instruction (4 sources) External interrupt IRQ 0 External interrupt IRQ 1 External interrupt IRQ 2 External interrupt IRQ 3 External interrupt IRQ 4 External ...
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Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset is the highest-priority exception. When the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules. Reset exception ...
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Figure 4.2 Reset Sequence (Modes 1 and 3) Section 4 Exception Handling Rev. 2.00 Sep 20, 2005 page 75 of 800 REJ09B0260-0200 ...
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Section 4 Exception Handling RES Address bus RD HWR , LWR High (1), (3) Address of reset exception handling vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset exception handling ...
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RES Internal address bus Internal read signal Internal write signal Internal data bus (16 bits wide) (1) Address of reset exception handling vector (H'0000) (2) Start address (contents of reset exception handling vector address) (3) First instruction of program Figure ...
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Section 4 Exception Handling The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), 16-bit timer, 8-bit timer, serial communication interface (SCI), and A/D converter. Each interrupt source has a separate vector address. NMI is the highest-priority ...
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Stack Status after Exception Handling Figure 4.6 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP–4 SP–3 SP–2 SP–1 SP (ER7) Stack area Before exception handling SP–4 SP–3 SP–2 SP–1 SP (ER7) Stack ...
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Section 4 Exception Handling 4.6 Notes on Stack Usage When accessing word data or longword data, the H8/3024 Group regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the ...
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SP TRAPA instruction executed SP set to H'FFFEFF Legend CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: The diagram illustrates modes Figure 4.7 Operation when SP Value is Odd CCR ...
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Section 4 Exception Handling Rev. 2.00 Sep 20, 2005 page 82 of 800 REJ09B0260-0200 ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The interrupt controller has the following features: Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt ...
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Section 5 Interrupt Controller 5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. ISCR NMI input IRQ input section ISR OVF TME . . . . . . . . . . TEI TEIE Interrupt controller ...
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Pin Configuration Table 5.1 lists the interrupt pins. Table 5.1 Interrupt Pins Name Nonmaskable interrupt External interrupt request Note the versions with on-chip flash memory, NMI input is sometimes disabled. For details see 17.9, ...
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Section 5 Interrupt Controller SYSCR is initialized to H' reset and in hardware standby mode not initialized in software standby mode. Bit 7 SSBY STS2 Initial value 0 Read/Write R/W Software standby Bit 3—User Bit Enable ...
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Interrupt Priority Register A (IPRA) IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRA7 IPRA6 Initial value 0 Read/Write R/W R/W Priority level A6 Selects the priority level of IRQ interrupt requests ...
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Section 5 Interrupt Controller Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ Bit 7 IPRA7 Description 0 IRQ interrupt requests have priority level 0 (low priority IRQ interrupt requests have priority level 1 (high priority) ...
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Bit 2—Priority Level A2 (IPRA2): Selects the priority level of 16-bit timer channel 0 interrupt requests. Bit 2 IPRA2 Description 0 16-bit timer channel 0 interrupt requests have priority level 0 (low priority) (Initial value) 1 16-bit timer channel 0 ...
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Section 5 Interrupt Controller Interrupt Priority Register B (IPRB) IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRB7 IPRB6 Initial value 0 Read/Write R/W R/W Priority level B6 Selects the priority level ...
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Bit 6—Priority Level B6 (IPRB6): Selects the priority level of 8-bit timer channel 2, 3 interrupt requests. Bit 6 IPRB6 Description 0 8-bit timer channel 2 and 3 interrupt requests have priority level 0 (low priority) 1 8-bit timer channel ...
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Section 5 Interrupt Controller 5.2.3 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ requests. Bit 7 — Initial value 0 Read/Write — Reserved bits Note: * Only 0 can be written, to ...
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IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ Bit 7 — — Initial value 0 Read/Write R/W R/W Reserved bits IER is initialized to H' reset and in hardware standby ...
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Section 5 Interrupt Controller 5.2.5 IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins Bit 7 ...
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Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ IRQ can be used to exit software standby mode. 2 NMI: NMI is the highest-priority interrupt and is ...
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Section 5 Interrupt Controller Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). IRQn input pin IRQnF Note Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector ...
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Table 5.3 Interrupt Sources, Vector Addresses, and Priority Interrupt Source Origin NMI External pins IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ 5 Reserved — WOVI Watchdog (interval timer) timer Reserved — ADI (A/D end) A/D IMIA0 ...
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Section 5 Interrupt Controller Interrupt Source Origin IMIA2 16-bit timer (compare match/ channel 2 input capture A2) IMIB2 (compare match/ input capture B2) OVI2 (overflow 2) Reserved — CMIA0 8-bit timer (compare match channel 0/1 A0) CMIB0 (compare match B0) ...
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Interrupt Source Origin ERI0 SCI (receive error 0) channel 0 RXI0 (receive data full 0) TXI0 (transmit data empty 0) TEI0 (transmit end 0) ERI1 SCI (receive error 1) channel 1 RXI1 (receive data full 1) TXI1 (transmit data empty ...
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Section 5 Interrupt Controller 5.4 Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3024 Group handles interrupts differently depending on the setting of the UE bit. When interrupts are controlled by the I bit. When ...
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Program execution state Interrupt requested? Yes No Priority level 1? Yes No IRQ 0 Yes No IRQ 1 Yes TEI1 Yes Save PC and CCR Read vector address Branch to interrupt service routine Figure 5.4 Process Up to Interrupt Acceptance ...
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Section 5 Interrupt Controller If an interrupt condition occurs and the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. When the interrupt controller receives one or more interrupt requests, it selects ...
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All interrupts are unmasked I 0 Figure 5.5 Interrupt Masking State Transitions (Example) Figure 5 flowchart showing how interrupts are accepted when interrupt condition occurs and the corresponding interrupt enable bit is ...
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Section 5 Interrupt Controller Priority level 1? IRQ 0 Yes IRQ Figure 5.6 Process Up to Interrupt Acceptance when Rev. 2.00 Sep 20, 2005 page 104 of 800 REJ09B0260-0200 Program execution state Interrupt requested? ...
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Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5.7 Interrupt Exception ...
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Section 5 Interrupt Controller 5.4.3 Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time No. Item ...
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Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed interrupt ...
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Section 5 Interrupt Controller 5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing ...
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Section 6 Bus Controller 6.1 Overview The H8/3024 Group has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set ...
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Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. Area Internal address bus decoder WAIT Internal signals CPU bus request signal CPU bus acknowledge signal Legend: ABWCR: Bus width control register ASTCR: ...
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Pin Configuration Table 6.1 summarizes the input/output pins of the bus controller. Table 6.1 Bus Controller Pins Name Abbreviation Chip select Address strobe A S Read R D High write ...
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Section 6 Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the bus controller’s registers. Table 6.2 Bus Controller Registers 1 Address * Name H'EE020 Bus width control register H'EE021 Access state control register H'EE022 Wait control register H H'EE023 Wait ...
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Bits 7 to 0—Area Bus Width Control (ABW7 to ABW0): These bits select 8-bit access or 16-bit access for the corresponding areas. Bits ABW7 to ABW0 Description 0 Areas are 16-bit ...
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Section 6 Bus Controller 6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. On-chip memory and registers are accessed in a fixed ...
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Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit ...
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Section 6 Bus Controller WCRL 7 6 Bit W31 W30 Initial value 1 1 Read/Write R/W R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area ...
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Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit ...
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Section 6 Bus Controller 6.2.4 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A enables or disables release of the bus to an external device. 7 Bit A23E Modes Initial ...
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Bit 6—Address 22 Enable (A22E): Enables PA Writing 0 in this bit enables A be modified and PA has its ordinary port functions. 5 Bit 6 A22E Description the input/output pin ...
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Section 6 Bus Controller 6.2.5 Bus Control Register (BCR Bit ICIS1 ICIS0 Initial value 1 1 Read/Write R/W R/W Note must not be written in bits BCR is an 8-bit readable/writable register that ...
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Bit 1—Area Division Unit Select (RDEA): Selects the memory map area division units. This bit is valid in modes 3, 4, and 5, and is invalid in modes and 7. Bit 1 RDEA Description 0 Area divisions ...
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Section 6 Bus Controller 6.2.6 Chip Select Control Register (CSCR) CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals ( output of a chip select ...
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Address Control Register (ADRCR) ADRCR is an 8-bit readable/writable register that selects either address update mode 1 or address update mode 2 as the address output method. Bit 7 6 — — Initial value 1 1 Read/Write — — ...
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Section 6 Bus Controller 6.3 Operation 6.3.1 Area Division The external address space is divided into areas Each area has a size of 128 kbytes in the 1- Mbyte modes Mbytes in the 16-Mbyte modes. ...
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H'000000 Area 0 2 Mbytes H'1FFFFF H'200000 Area 1 2 Mbytes H'3FFFFF H'400000 Area 2 2 Mbytes H'5FFFFF H'600000 Area 3 2 Mbytes H'7FFFFF H'800000 Area 4 2 Mbytes H'9FFFFF H'A00000 Area 5 2 Mbytes H'BFFFFF H'C00000 Area 6 2 ...
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Section 6 Bus Controller H'000000 H'1FFFFF H'200000 H'3FFFFF H'400000 H'5FFFFF H'600000 H'7FFFFF H'800000 H'9FFFFF H'A00000 H'BFFFFF H'C00000 H'DFFFFF H'E00000 H'FEE000 Internal I/O registers (1) H'FEE0FF H'FEE100 H'FF7FFF H'FF8000 H'FF8FFF H'FF9000 H'FFDF1F H'FFDF20 H'FFFEFF H'FFFF00 H'FFFF1F H'FFFF20 Internal I/O registers (2) ...
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Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and registers are fixed, and ...
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Section 6 Bus Controller Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH/WCRL ABWn ASTn Wn1 0 0 — — Note 6.3.3 Memory ...
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Chip Select Signals For each of areas the H8/3024 Group can output a chip select signal ( low when the corresponding area is selected in expanded mode. Figure 6.4 shows the output timing ...
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Section 6 Bus Controller 6.3.5 Address Output Method The H8/3024 Group provides a choice of two address update methods: either the same method as in the previous H8/300H Series (address update mode 1 method in which address updating ...
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Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data Size and Data Alignment ...
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Section 6 Bus Controller 16-Bit Access Areas: Figure 6.7 illustrates data alignment control for 16-bit access areas. With 16-bit access areas, the upper data bus (D accesses. The amount of data that can be accessed at one time is one ...
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Table 6.4 Data Buses Used and Valid Strobes Access Read/ Area Size Write 8-bit access Byte Read area Write 16-bit access Byte Read area Write Word Read Write Notes: 1. Undetermined data means that unpredictable data is output. 2. Invalid ...
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Section 6 Bus Controller 6.4.5 Basic Bus Control Signal Timing 8-Bit, Three-State-Access Areas: Figure 6.8 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper data bus (D pin is always high. Wait states can be ...
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Two-State-Access Areas: Figure 6.9 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper data bus (D pin is always high. Wait states cannot be inserted. Address bus Read access Write access Note ...
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Section 6 Bus Controller 16-Bit, Three-State-Access Areas: Figures 6.10 to 6.12 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper data bus (D accesses to even addresses and the lower data bus ...
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Address bus Read access HWR LWR Write access Note Figure 6.11 ...
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Section 6 Bus Controller Address bus Read access HWR LWR Write access Note Figure 6.12 ...
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Two-State-Access Areas: Figures 6.13 to 6.15 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper data bus (D even addresses and the lower data bus (D be inserted. Address bus Read ...
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Section 6 Bus Controller Address bus Read access Write access Note Figure 6.14 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2) Rev. 2.00 Sep 20, 2005 page 140 of 800 REJ09B0260-0200 Bus cycle T ...
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Address bus Read access Write access Note Figure 6.15 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3) 6.4.6 Wait Control When accessing external space, the H8/3024 Group can extend the bus cycle by inserting ...
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Section 6 Bus Controller Pin Wait Insertion: Setting the WAITE bit in BCR to 1 enables wait insertion by means of the pin. When external space is accessed in this state, a program wait is first inserted. If the W ...
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Idle Cycle 6.5.1 Operation When the H8/3024 Group chip accesses external space, it can insert a 1-state idle cycle (T between bus cycles in the following cases: when read accesses between different areas occur consecutively, and when a write ...
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Section 6 Bus Controller Write after Read external write occurs after an external read while the ICIS0 bit is set BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.18 ...
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Usage Note: When non-insertion of an idle cycle is specified, the rise (negation) of (assertion) of may occur simultaneously. Figure 6.19 shows an example of the operation this case. If consecutive reads to a different external ...
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Section 6 Bus Controller 6.5.2 Pin States in Idle Cycle Table 6.5 shows the pin states in an idle cycle. Table 6.5 Pin States in Idle Cycle Pins ...
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Operation CPU: The CPU is the lowest-priority bus master external bus master requests the bus while the CPU has the bus right, the bus arbiter transfers the bus right to the bus master that requested it. The ...
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Section 6 Bus Controller T Address bus Data bus AS RD HWR, LWR BREQ BACK Figure 6.20 Example of External Bus Master Operation When making a transition to software standby mode, if there is contention with a bus request from ...
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Register and Pin Input Timing 6.7.1 Register Write Timing ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR, WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.21 shows the timing when an ...
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Section 6 Bus Controller BRCR Write Timing: Data written to BRCR to switch between A generic input or output takes effect starting from the T 6.23 shows the timing when a pin is changed from generic input to A Address ...
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Overview The H8/3024 Group has 10 input/output ports (ports and B) and one input- only port (port 7). Table 7.1 summarizes the port functions. The pins in each port are ...
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Section 7 I/O Ports Port Description Pins Port 4 • 8-bit I port • Built-in input pull-up transistors Port 5 • 4-bit I ...
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Port Description Pins Port 8 • 5-bit I port • have Schmitt P8 ...
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Section 7 I/O Ports Port Description Pins Port B • 8-bit I port TMIO / ...
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Port 1 7.2.1 Overview Port 8-bit input/output port also used for address output, with the pin configuration shown in figure 7.1. The pin functions differ according to the operating mode. In modes (expanded ...
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Section 7 I/O Ports 7.2.2 Register Descriptions Table 7.2 summarizes the registers of port 1. Table 7.2 Port 1 Registers Address * Name H'EE000 Port 1 data direction register P1DDR H'FFFD0 Port 1 data register Note: * Lower 20 bits ...
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P1DDR is initialized to H'FF in modes and to H'00 in modes reset and in hardware standby mode. In sofware standby mode it retains its previous setting. Therefore transition is ...
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Section 7 I/O Ports 7.3 Port 2 7.3.1 Overview Port 8-bit input/output port which also has an address output function. It’s pin configuration is shown in figure 7.2. The pin functions differ according to the operating mode. ...
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Register Descriptions Table 7.3 summarizes the registers of port 2. Table 7.3 Port 2 Registers Address * Name H'EE001 Port 2 data direction register H'FFFD1 Port 2 data register H'EE03C Port 2 input pull-up MOS control register Note: * ...
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Section 7 I/O Ports In modes P2DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P2DDR is initialized to H'FF in modes and to H'00 in modes ...