HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 399
HD64F3026X25
Manufacturer Part Number
HD64F3026X25
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.DF3026XBL25V.pdf
(843 pages)
Specifications of HD64F3026X25
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Part Number:
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Bit 7
C/
0
1
Bit 7
GM
0
1
Note: etu: Elementary time unit (time required to transmit one bit)
Bit 6—Character Length (CHR): Selects 7-bit or 8-bits data length in asynchronous mode. In
synchronous mode, the data length is 8 bits regardless of the CHR setting.
Bit 6
CHR
0
1
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
Bit 5—Parity Enable (PE): In asynchronous mode, this bit enables or disables the addition of a
parity bit to transmit data, and the checking of the parity bit in receive data. In synchronous mode,
the parity bit is neither added nor checked, regardless of the PE bit setting.
Bit 5
PE
0
1
Note: * When PE bit is set to 1, an even or odd parity bit is added to transmit data according to the
A
For Serial Communication Interface (SMIF Bit in SCMR Cleared to 0)
Selects whether the SCI operates in asynchronous or synchronous mode.
For Smart Card Interface (SMIF Bit in SCMR Set to 1)
Selects GSM mode for the smart card interface.
even or odd parity mode selection by the O/
checked to see that it matches the even or odd mode selected by the O/
Description
Asynchronous mode
Synchronous mode
Description
The TEND flag is set 12.5 etu after the start bit
The TEND flag is set 11.0 etu after the start bit
Description
8-bit data
7-bit data *
Description
Parity bit not added or checked
Parity bit added and checked *
E
bit, and the parity bit in receive data is
Section 12 Serial Communication Interface
Rev. 2.00 Sep 20, 2005 page 359 of 800
E
REJ09B0260-0200
bit.
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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