HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 326
HD64F3026X25
Manufacturer Part Number
HD64F3026X25
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.DF3026XBL25V.pdf
(843 pages)
Specifications of HD64F3026X25
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3026X25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 9 8-Bit Timers
ICE Bit in
8TCSR1
(8TCSR3)
0
1
Bits 1 and 0—Output Select A1 and A0 (OS1, OS0): These bits select the compare match A
output level.
Bit 1
OS1
0
1
Rev. 2.00 Sep 20, 2005 page 286 of 800
REJ09B0260-0200
When the compare match register function is used, the timer output priority order is: toggle
output > 1 output > 0 output.
If compare match A and B occur simultaneously, the output changes in accordance with the
higher-priority compare match.
When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
When the compare match register function is used, the timer output priority order is: toggle
output > 1 output > 0 output.
If compare match A and B occur simultaneously, the output changes in accordance with the
higher-priority compare match.
When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
Bit 0
OS0
0
1
0
1
Bit 3
OIS3
0
1
0
1
Description
No change when compare match A occurs
0 is output when compare match A occurs
1 is output when compare match A occurs
Output is inverted when compare match A occurs (toggle output)
Bit 2
OIS2
0
1
0
1
0
1
0
1
Description
No change when compare match B occurs
0 is output when compare match B occurs
1 is output when compare match B occurs
Output is inverted when compare match B occurs (toggle output)
TCORB input capture on rising edge
TCORB input capture on falling edge
TCORB input capture on both rising and falling edges
(Initial value)
(Initial value)
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