HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 114

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 4 Exception Handling
4.2
4.2.1
A reset is the highest-priority exception. When the
chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the
on-chip supporting modules. Reset exception handling begins when the
low to high.
The chip can also be reset by overflow of the watchdog timer. For details see section 11,
Watchdog Timer.
4.2.2
The chip enters the reset state when the
To ensure that the chip is reset, hold the
chip during operation, hold the
with on-chip flash memory, the
appendix D.2, Pin States at Reset, for the states of the pins in the reset state.
When the
exception handling as follows.
Figure 4.2 shows the reset sequence in modes 1 and 3. Figure 4.3 shows the reset sequence in
modes 2 and 4. Figure 4.4 shows the reset sequence in mode 6.
Rev. 2.00 Sep 20, 2005 page 74 of 800
REJ09B0260-0200
The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit is set to 1 in CCR.
The contents of the reset vector address (H'0000 to H'0003 in advanced mode, H'0000 to
H'0001 in normal mode) are read, and program execution starts from the address indicated in
the vector address.
Reset
Overview
Reset Sequence
R E S
pin goes high after being held low for the necessary time, the chip starts reset
R E S
R E S
pin low for at least 10 system clock (ø) cycles. In the versions
pin must be held low for at least 20 system clock cycles. See
R E S
R E S
pin goes low.
pin low for at least 20 ms at power-up. To reset the
R E S
pin goes low, all processing halts and the
R E S
pin changes from