HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 160

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 Bus Controller
6.2.5
Bit
Initial value
Read/Write
Note: * 1 must not be written in bits 5 to 3.
BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the
area division unit, and enables or disables
BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted
between bus cycles in case of consecutive external read cycles for different areas.
Bit 7
ICIS1
0
1
Bit 6—Idle Cycle Insertion 0 (ICIS0): Selects whether one idle cycle state is to be inserted
between bus cycles in case of consecutive external read and write cycles.
Bit 6
ICIS0
0
1
Bits 5 to 3—Reserved (must not be set to 1): These bits can be read and written, but must not be
set to 1. Normal operation cannot be guaranteed if 1 is written in these bits.
Bit 2—Reserved: Read-only bit, always read as 1.
Rev. 2.00 Sep 20, 2005 page 120 of 800
REJ09B0260-0200
Bus Control Register (BCR)
ICIS1
R/W
7
1
Description
No idle cycle inserted in case of consecutive external read cycles for different
areas
Idle cycle inserted in case of consecutive external read cycles for different
areas
Description
No idle cycle inserted in case of consecutive external read and write cycles
Idle cycle inserted in case of consecutive external read and write cycles
ICIS0
R/W
6
1
0 *
—
—
5
W A I T
—
0 *
—
4
pin input.
0 *
—
—
3
—
—
2
1
RDEA
R/W
1
1
(Initial value)
(Initial value)
WAITE
R/W
0
0