HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 610

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 18 Flash Memory [H8/3024F-ZTAT Version]
Notes on Use of Emulation in RAM:
1. Flash write enable (FWE) application and releasing
2. NMI input disabling conditions
3. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of
4. A RAM area cannot be erased by execution of software in accordance with the erase algorithm
5. Block area EB0 contains the vector table. When performing RAM emulation, the vector table
18.9
All interrupts, including NMI input, should be disabled while flash memory is being programmed
or erased (while the P bit or E bit is set in FLMCR1), and while the boot program is executing in
boot mode *
1. NMI input during programming or erasing might cause a violation of the programming or
2. In the NMI exception handling sequence during programming or erasing, the vector would not
3. If NMI input occurred during boot program execution, it would not be possible to execute the
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REJ09B0260-0200
As in on-board program mode, care is required when applying and releasing FWE to prevent
erroneous programming or erasing. To prevent erroneous programming and erasing due to
program runaway during FWE application, in particular, the watchdog timer should be set
when the PSU, P, ESU, or E bit is set to 1 in FLMCR1, even while the emulation function is
being used. For details, see section 18.11, Flash Memory Programming and Erasing
Precautions.
When the emulation function is used, NMI input is disabled when the P bit or E bit is set to 1
in FLMCR1, in the same way as with normal programming and erasing.
The P and E bits are cleared by a reset (including a watchdog timer reset), in standby mode,
when a high level is not being input to the FWE pin, or when the SWE bit in FLMCR1 is 0
while a high level is being input to the FWE pin.
the value of RAM2 to RAM0 (emulation protection). In this state, setting the P or E bit in
FLMCR1 will not cause a transition to program mode or erase mode. When actually
programming or erasing a flash memory area, the RAMS bit should be cleared to 0.
while flash memory emulation in RAM is being used.
is needed in the overlap RAM.
erasing algorithm, with the result that normal operation could not be assured.
be read correctly *
normal boot mode sequence.
NMI Input Disabling Conditions
1
, to give priority to the program or erase operation. There are three reasons for this:
2
, possibly resulting in MCU runaway.