HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 773

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

8TCSR2—Timer Control/Status Register 2
8TCSR3—Timer Control/Status Register 3
8TCSR2
8TCSR3
Note: * Only 0 can be written to bits 7 to 5 to clear these flags.
Initial value
Read/Write
Initial value
Read/Write
Bit
Bit
Compare match/input capture flag B
0
1
R/(W)*
R/(W)*
CMFB
CMFB
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB.
[Setting conditions]
• 8TCNT = TCORB
• The 8TCNT value is transferred to TCORB by an input capture signal when
7
0
7
0
TCORB functions as an input capture register.
Compare match/input capture flag A
0
1
R/(W)*
R/(W)*
CMFA
CMFA
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA.
[Setting condition]
8TCNT = TCORA
6
0
6
0
Timer overflow flag
0
1
R/(W)*
R/(W)*
OVF
OVF
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF.
[Setting condition]
8TCNT overflows from H'FF to H'00.
5
0
5
0
Input capture enable
0
1
R/W
ICE
—
4
1
4
0
TCORB is a compare match register
TCORB is an input capture register
Output/input capture edge select B3 and B2
8TCSR3
ICE in
OIS3
OIS3
0
1
R/W
R/W
3
0
3
0
Bit 3
OIS3
0
1
0
1
Bit 1
Output select A1 and A0
OS1
H'FFF92
H'FFF93
OIS2
OIS2
Rev. 2.00 Sep 20, 2005 page 733 of 800
R/W
R/W
0
1
2
0
2
0
Bit 3
OIS2
Bit 0
OS0
0
1
0
1
0
1
0
0
1
0
1
No change at compare match B
0 output at compare match B
1 output at compare match B
Output toggles at compare match B
TCORB input capture on rising edge
TCORB input capture on falling edge
TCORB input capture on both rising and
falling edges
OS1
R/W
OS1
R/W
No change at compare match A
0 output at compare match A
1 output at compare match A
Output toggles at compare match A
Appendix B Internal I/O Registers
1
0
1
0
OS0
R/W
OS0
R/W
Description
0
0
0
0
Description
8-bit timer channel 2
8-bit timer channel 3
REJ09B0260-0200