HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 599

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5. The period for which the P bit in FLMCR1 is set (the write pulse width) should be changed
Item
Wait time after
P bit setting
Note: * Additional programming processing is necessary only when the reprogramming loop count
6. The program/program-verify flowchart for the H8/3024F-ZTAT version is shown in figure
c. If programming of other bits is incomplete in the 128 bytes, reprogramming processing
according to the degree of progress through the program/program-verify procedure. For
detailed wait time specifications, see section 21.2.6, Flash Memory Characteristics.
18.11.
To cover the points noted above, bits on which reprogramming processing is to be executed,
and bits on which additional programming is to be executed, must be determined as shown
below.
Since reprogram data and additional-programming data vary according to the progress of the
programming procedure, it is recommended that the following data storage areas (128 bytes
each) be provided in RAM.
When programming is completed at an early stage in the program/program-verify
procedure:
If programming is completed in the 1st to 6th reprogramming processing loop, additional
programming should be performed on the relevant bits. Additional programming should
only be performed on bits which first return 0 in a verify-read in certain reprogramming
processing.
When programming is completed at a late stage in the program/program-verify procedure:
If programming is completed in the 7th or later reprogramming processing loop, additional
programming is not necessary for the relevant bits.
should be executed. If a bit for which programming has been judged to be completed is
read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit.
(n) is 1 to 6.
Symbol
t
sp
Item
When reprogramming loop count (n) is 1 to 6
When reprogramming loop count (n) is 7 or more
In case of additional programming processing *
Section 18 Flash Memory [H8/3024F-ZTAT Version]
Rev. 2.00 Sep 20, 2005 page 559 of 800
REJ09B0260-0200
Symbol
t
t
t
sp
sp
sp
30
200
10