HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 371

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 10.5 shows
an example in which the TPC is used for cyclic five-phase pulse output.
GRA
H'0000
NDRB
PBDR
TP
TP
TP
TP
TP
1.
2.
3.
4.
TCNT value
15
14
13
12
11
The 16-bit timer channel to be used as the output trigger channel is set up so that GRA is an output
compare register and the counter will be cleared by compare match A. The trigger period is set in GRA.
The IMIEA bit is set to 1 in TISRA to enable the compare match A interrupt.
H'F8 is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in
TPCR to select compare match in the 16-bit timer channel set up in step 1 as the output trigger.
Output data H'80 is written in NDRB.
The timer counter in this 16-bit timer channel is started. When compare match A occurs, the NDRB
contents are transferred to PBDR and output. The compare match/input capture A (IMFA) interrupt
service routine writes the next output data (H'C0) in NDRB.
Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing
H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88… at successive IMFA interrupts.
00
80
Figure 10.5 Normal TPC Output Example (Five-Phase Pulse Output)
80
TCNT
C0
C0
40
40
60
Compare match
60
20
Section 10 Programmable Timing Pattern Controller (TPC)
20
30
30
10
10
Rev. 2.00 Sep 20, 2005 page 331 of 800
18
18
08
08
88
88
80
REJ09B0260-0200
80
C0
C0
40
Time