HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 258

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 16-Bit Timer
In phase counting mode, external clock edge selection by bits CKEG1 and CKEG0 in 16TCR2
and counter clock selection by bits TPSC2 to TPSC0 are invalid, and the above phase counting
mode operations take precedence.
The counter clearing condition selected by the CCLR1 and CCLR0 bits in 16TCR2 and the
compare match/input capture settings and interrupt functions of TIOR2, TISRA, TISRB, TISRC
remain effective in phase counting mode.
Bit 5—Flag Direction (FDIR): Designates the setting condition for the OVF flag in TISRC. The
FDIR designation is valid in all modes in channel 2.
Bit 5
FDIR
0
1
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1.
Bit 2—PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode.
Bit 2
PWM2
0
1
When bit PWM2 is set to 1 to select PWM mode, pin TIOCA
output goes to 1 at compare match with GRA2, and to 0 at compare match with GRB2.
Bit 1—PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode.
Bit 1
PWM1
0
1
When bit PWM1 is set to 1 to select PWM mode, pin TIOCA
output goes to 1 at compare match with GRA1, and to 0 at compare match with GRB1.
Rev. 2.00 Sep 20, 2005 page 218 of 800
REJ09B0260-0200
Description
OVF is set to 1 in TISRC when 16TCNT2 overflows or underflows
OVF is set to 1 in TISRC when 16TCNT2 overflows
Description
Channel 2 operates normally
Channel 2 operates in PWM mode
Description
Channel 1 operates normally
Channel 1 operates in PWM mode
2
1
becomes a PWM output pin. The
becomes a PWM output pin. The
(Initial value)
(Initial value)
(Initial value)