HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 102

MCU 3V 256K 100-TQFP

HD64F3026X25

Manufacturer Part Number
HD64F3026X25
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3026X25

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3026X25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 3 MCU Operating Modes
Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and
bus control signals (
in the high-impedance state in software standby mode.
Bit 1
SSOE
0
1
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by the rising edge of the
Bit 0
RAME
0
1
3.4
3.4.1
Ports 1, 2, and 5 function as address pins A
address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least
one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.2
Ports 1, 2, and 5 function as address pins A
address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all
areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits.
Rev. 2.00 Sep 20, 2005 page 62 of 800
REJ09B0260-0200
Operating Mode Descriptions
Mode 1
Mode 2
Description
In software standby mode, the address bus and bus control signals are all high-
impedance
In software standby mode, the address bus retains its output state and bus control
signals are fixed high
Description
On-chip RAM is disabled
On-chip RAM is enabled
C S
0
to
C S
7
,
A S
R E S
,
R D
(Initial value)
,
signal. It is not initialized in software standby mode.
H W R
19
19
to A
to A
,
L W R
0
0
, permitting access to a maximum 1-Mbyte
, permitting access to a maximum 1-Mbyte
) are kept as outputs or fixed high, or placed
(Initial value)

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