HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 334

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 9 8-Bit Timers
9.4.5
If bits CKS2 to CKS0 are set to (100) in either 8TCR0 or 8TCR1, the 8-bit timers of channels 0
and 1 are cascaded. With this configuration, the two timers can be used as a single 16-bit timer
(16-bit timer mode), or channel 0 8-bit timer compare matches can be counted in channel 1
(compare match count mode). Similarly, if bits CKS2 to CKS0 are set to (100) in either 8TCR2 or
8TCR3, the 8-bit timers of channels 2 and 3 are cascaded. With this configuration, the two timers
can be used as a single 16-bit timer (16-bit timer mode),or channel 2 8-bit timer compare matches
can be counted in channel 3 (compare match count mode). In this case, the timer operates as
below.
16-Bit Count Mode
Rev. 2.00 Sep 20, 2005 page 294 of 800
REJ09B0260-0200
Channels 0 and 1:
When bits CKS2 to CKS0 are set to (100) in 8TCR0, the timer functions as a single 16-bit
timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
Setting when Compare Match Occurs
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•
•
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Setting when Input Capture Occurs
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Counter Clear Specification
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OVF Flag Operation
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Operation with Cascaded Connection
The CMFA or CMFB flag is set to 1 in 8TCSR0 when a 16-bit compare match occurs.
The CMFA or CMFB flag is set to 1 in 8TCSR1 when a lower 8-bit compare match
occurs.
TMO
accordance with the 16-bit compare match conditions.
TMIO
accordance with the lower 8-bit compare match conditions.
The CMFB flag is set to 1 in 8TCSR0 and 8TCSR1 when the ICE bit is 1 in TCSR1
and input capture occurs.
TMIO
in 8TCSR0.
If counter clear on compare match or input capture has been selected by the CCLR1
and CCLR0 bits in 8TCR0, the 16-bit counter (both 8TCNT0 and 8TCNT1) is cleared.
The settings of the CCLR1 and CCLR0 bits in 8TCR1 are ignored. The lower 8 bits
cannot be cleared independently.
The OVF flag is set to 1 in 8TCSR0 when the 16-bit counter (8TCNT0 and 8TCNT1)
overflows (from H'FFFF to H'0000).
The OVF flag is set to 1 in 8TCSR1 when the 8-bit counter (8TCNT1) overflows (from
H'FF to H'00).
0
1
1
pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR0 is in
pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR1 is in
pin input capture input signal edge detection is selected by bits OIS3 and OIS2