HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 443

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

In transmitting serial data, the SCI operates as follows.
Figure 12.17 shows an example of SCI transmit operation.
Receiving Serial Data (Synchronous Mode): Figure 12.18 shows a sample flowchart for
receiving serial data and indicates the procedure to follow. When switching from asynchronous to
synchronous mode. make sure that the ORER, PER, and FER flags are cleared to 0. If the FER or
Serial clock
Serial data
TDRE
TEND
The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock
source is selected, the SCI outputs data in synchronization with the input clock. Data is output
from the TxD pin in order from LSB (bit 0) to MSB (bit 7).
The SCI checks the TDRE flag when it outputs the MSB (bit 7). If the TDRE flag is 0, the
SCI loads data from TDR into TSR and begins serial transmission of the next frame. If the
TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, and after transmitting the MSB, holds
the TxD pin in the MSB state. If the TEIE bit is set to 1 in SCR, a transmit-end interrupt (TEI)
is requested at this time.
After the end of serial transmission, the SCK pin is held in a constant state.
TXI interrupt
request
Figure 12.17 Example of SCI Transmit Operation
TXI interrupt handler
writes data in TDR
and clears TDRE
flag to 0
Bit 0
Transmit direction
Bit 1
1 frame
TXI interrupt
request
Bit 7
Section 12 Serial Communication Interface
Bit 0
Rev. 2.00 Sep 20, 2005 page 403 of 800
Bit 1
REJ09B0260-0200
Bit 6
TEI interrupt
request
Bit 7