PIC18F46K22-I/MV Microchip Technology, PIC18F46K22-I/MV Datasheet - Page 108

• Manufacturer Part Number: PIC18F46K22-I/MV
• Description: 64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46K22-I/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-UFQFN Exposed Pad
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Number Of Programmable I/os: 36
• Number Of Timers: 3 x 8-bit. 4 x 16-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18(L)F2X/4XK22
7.6
Data EEPROM memory has its own code-protect bits
in Configuration Words. External read and write
operations are disabled if code protection is enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect Configuration bit. Refer to
“Special Features of the CPU”
information.
7.7
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been implemented. On power-up, the WREN bit is
cleared. In addition, writes to the EEPROM are blocked
during the Power-up Timer period (T
EXAMPLE 7-3:
DS41412D-page 108
Loop
Operation During Code-Protect
Protection Against Spurious Write
CLRF
BCF
BCF
BCF
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ
BRA
BCF
BSF
EEADR
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
EECON1, RD
55h
EECON2
0AAh
EECON2
EECON1, WR
EECON1, WR
$-2
EEADR, F
LOOP
EECON1, WREN
INTCON, GIE
DATA EEPROM REFRESH ROUTINE
PWRT
for additional
Section 24.0
).
; Start at address 0
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write 0AAh
; Set WR bit to begin write
; Wait for write to complete
; Increment address
; Not zero, do it again
; Disable writes
; Enable interrupts
Preliminary
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
7.8
The data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated often).
When variables in one section change frequently, while
variables in another section do not change, it is possible
to exceed the total number of write cycles to the
EEPROM without exceeding the total number of write
cycles to a single byte. Refer to the Data EEPROM
Memory parameters in
Characteristics”
then an array refresh must be performed. For this
reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
A simple data EEPROM refresh routine is shown in
Example
Note:
Using the Data EEPROM
7-3.
If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification.
for write cycle limits. If this is the case,
 2010 Microchip Technology Inc.
Section 27.0 “Electrical