PIC18F46K22-I/MV Microchip Technology, PIC18F46K22-I/MV Datasheet - Page 295

• Manufacturer Part Number: PIC18F46K22-I/MV
• Description: 64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46K22-I/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-UFQFN Exposed Pad
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Number Of Programmable I/os: 36
• Number Of Timers: 3 x 8-bit. 4 x 16-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.2
17.2.1
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will, depend-
ing on the ACQT bits of the ADCON2 register, either
immediately start the Analog-to-Digital conversion or
start an acquisition delay followed by the Analog-to-
Digital conversion.
FIGURE 17-3:
FIGURE 17-4:
 2010 Microchip Technology Inc.
(Holding capacitor continues
acquiring input)
Set GO bit
1
T
CY
Set GO bit
T
ADC Operation
Holding capacitor is disconnected from analog input (typically 100 ns)
ACQT
Acquisition
Automatic
- T
STARTING A CONVERSION
2
Time
AD
Conversion starts
Cycles
T
AD
3
1 T
A/D CONVERSION T
A/D CONVERSION T
AD
b9
4
2 T
Conversion starts
(Holding capacitor is disconnected from analog input)
AD
b8
1
3 T
AD
b9
2
b7
4 T
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
AD
b8
3
b6
AD
AD
5 T
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
CYCLES (A
CYCLES (A
Preliminary
AD
b5
b7
4
6 T
T
AD
b4
5
b6
AD
7 T
Cycles
Figure 17-3
after the GO bit has been set and the ACQT<2:0> bits
are cleared. A conversion is started after the following
instruction to allow entry into SLEEP mode before the
conversion begins.
Figure 17-4
after the GO bit has been set and the ACQT<2:0> bits
are set to ‘010’ which selects a 4 T
before the conversion starts.
CQT
AD
CQT
b3
b5
Note:
6
PIC18(L)F2X/4XK22
8
<2:0> = 000, T
<2:0> = 010, T
T
AD
b4
b2
7
9 T
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to
sion
shows the operation of the A/D converter
shows the operation of the A/D converter
AD
b3
8
b1
Procedure”.
10
T
Section 17.2.10 “A/D Conver-
AD
ACQ
b0
b2
9
ACQ
11
2 T
= 0)
10
= 4 T
Discharge
b1
AD
AD
AD
b0
DS41412D-page 295
11
)
acquisition time
2 T
Discharge
AD