PIC18F46K22-I/MV Microchip Technology, PIC18F46K22-I/MV Datasheet - Page 361

64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE

PIC18F46K22-I/MV

Manufacturer Part Number
PIC18F46K22-I/MV
Description
64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet

Specifications of PIC18F46K22-I/MV

Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 30x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-UFQFN Exposed Pad
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
4 KB
Number Of Programmable I/os
36
Number Of Timers
3 x 8-bit. 4 x 16-bit
Operating Supply Voltage
1.8 V to 5.5 V
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
24.2.1
Register 24-14
readable and writable register which contains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
REGISTER 24-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER
TABLE 24-3:
TABLE 24-4:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
Note 1:
RCON
WDTCON
Legend: — = unimplemented, read as ‘0’. Shaded bits are not used by the Watchdog Timer.
CONFIG2H
Legend: — = unimplemented, read as ‘0’. Shaded bits are not used by the Watchdog Timer.
Name
Name
U-0
This bit has no effect if the Configuration bit, WDTEN, is enabled.
CONTROL REGISTER
shows the WDTCON register. This is a
Unimplemented: Read as ‘0’
SWDTEN: Software Enable or Disable the Watchdog Timer bit
1 = WDT is turned on
0 = WDT is turned off (Reset value)
IPEN
Bit 7
Bit 7
REGISTERS ASSOCIATED WITH WATCHDOG TIMER
CONFIGURATION REGISTERS ASSOCIATED WITH WATCHDOG TIMER
U-0
SBOREN
Bit 6
Bit 6
W = Writable bit
‘1’ = Bit is set
U-0
Bit 5
Bit 5
U-0
Preliminary
Bit 4
Bit 4
RI
WDPS<3:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Bit 3
Bit 3
U-0
TO
PIC18(L)F2X/4XK22
Bit 2
Bit 2
PD
(1)
U-0
Bit 1
POR
Bit 1
WDTEN<1:0>
x = Bit is unknown
U-0
SWDTEN
Bit 0
BOR
Bit 0
DS41412D-page 361
SWDTEN
R/W-0
on Page
on Page
Values
Values
Reset
Reset
361
353
60
bit 0
(1)

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