PIC18F46K22-I/MV Microchip Technology, PIC18F46K22-I/MV Datasheet - Page 269

• Manufacturer Part Number: PIC18F46K22-I/MV
• Description: 64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46K22-I/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-UFQFN Exposed Pad
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Number Of Programmable I/os: 36
• Number Of Timers: 3 x 8-bit. 4 x 16-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.1.2.4
The RCxIF interrupt flag bit of the PIR1/PIR3 register is
set whenever the EUSART receiver is enabled and
there is an unread character in the receive FIFO. The
RCxIF interrupt flag bit is read-only, it cannot be set or
cleared by software.
RCxIF interrupts are enabled by setting the following
bits:
• RCxIE interrupt enable bit of the PIE1/PIE3
• PEIE/GIEL peripheral interrupt enable bit of the
• GIE/GIEH global interrupt enable bit of the
The RCxIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
16.1.2.5
Each character in the receive FIFO buffer has a
corresponding framing error Status bit. A framing error
indicates that a Stop bit was not seen at the expected
time. The framing error status is accessed via the
FERR bit of the RCSTAx register. The FERR bit
represents the status of the top unread character in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCREG.x
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCSTAx register which resets the EUSART.
Clearing the CREN bit of the RCSTAx register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
16.1.2.6
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCSTAx register is
set. The characters already in the FIFO buffer can be
read but no additional characters will be received until
the error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTAx register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTAx register.
 2010 Microchip Technology Inc.
register
INTCON register
INTCON register
Note:
If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCREGx will not clear the FERR
bit.
Receive Interrupts
Receive Framing Error
Receive Overrun Error
Preliminary
16.1.2.7
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTAx register is set, the EUSART
will shift 9 bits into the RSR for each character
received. The RX9D bit of the RCSTAx register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREGx.
16.1.2.8
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCSTAx
register.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
receive FIFO buffer, thereby setting the RCxIF interrupt
bit. All other characters will be ignored.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit occurs. When user software detects the end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
PIC18(L)F2X/4XK22
Receiving 9-bit Characters
Address Detection
DS41412D-page 269