PIC18F46K22-I/MV Microchip Technology, PIC18F46K22-I/MV Datasheet - Page 183

• Manufacturer Part Number: PIC18F46K22-I/MV
• Description: 64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46K22-I/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-UFQFN Exposed Pad
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Number Of Programmable I/os: 36
• Number Of Timers: 3 x 8-bit. 4 x 16-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 14-5:
TABLE 14-6:
 2010 Microchip Technology Inc.
IPR1
IPR2
IPR4
PIE1
PIE2
PIE4
PIR1
PIR2
PIR4
PMD0
PMD1
T1CON
T1GCON
T3CON
T3GCON
T5CON
T5GCON
TMR1H
TMR1L
TMR3H
TMR3L
TMR5H
TMR5L
TRISA
TRISB
TRISC
TRISD
TRISE
Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode.
Note
CONFIG3H
Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode.
Name
Name
(1)
1:
These registers/bits are available on PIC18(L)F4XK22 devices.
MCLRE
UART2MD
MSSP2MD
TMR1GE
TMR3GE
TMR5GE
Bit 7
OSCFIP
OSCFIE
OSCFIF
TRISA7
TRISB7
TRISC7
TRISD7
WPUE3
Bit 7
REGISTERS ASSOCIATED WITH COMPARE (CONTINUED)
CONFIGURATION REGISTERS ASSOCIATED WITH CAPTURE
—
—
—
—
—
—
TMR1CS<1:0>
TMR3CS<1:0>
TMR5CS<1:0>
MSSP1MD
Bit 6
UART1MD
T1GPOL
T3GPOL
T5GPOL
—
TRISA6
TRISB6
TRISC6
TRISD6
ADIP
ADIE
Bit 6
C1IP
C1IE
ADIF
C1IF
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Least Significant Byte of the 16-bit TMR5 Register
—
—
—
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR5 Register
—
P2BMX
Bit 5
TMR6MD
TRISA5
TRISB5
TRISC5
TRISD5
T1GTM
T3GTM
T5GTM
RC1IP
RC1IE
RC1IF
Bit 5
C2IP
C2IE
C2IF
—
—
—
—
—
T1CKPS<1:0>
T3CKPS<1:0>
T5CKPS<1:0>
T3CMX
Bit 4
Preliminary
TMR5MD
CCP5MD
T1GSPM
T3GSPM
T5GSPM
TRISA4
TRISB4
TRISC4
TRISD4
TX1IP
TX1IE
TX1IF
EEIP
EEIE
EEIF
Bit 4
—
—
—
—
HFOFST
Bit 3
T1GGO/DONE
T3GGO/DONE
T5GGO/DONE
T1SOSCEN
T3SOSCEN
T5SOSCEN
TMR4MD
CCP4MD
TRISC3
TRISD3
SSP1IP
BCL1IP
SSP1IE
BCL1IE
SSP1IF
BCL1IF
TRISA3
TRISB3
Bit 3
PIC18(L)F2X/4XK22
—
—
—
—
CCP3MX
Bit 2
TRISE2
TMR3MD
CCP3MD
T1SYNC
T3SYNC
T5SYNC
T1GVAL
T3GVAL
T5GVAL
CCP1IP
HLVDIP
CCP5IP
CCP1IE
HLVDIE
CCP5IE
CCP1IF
CCP5IF
TRISA2
TRISB2
TRISC2
TRISD2
HLVDIF
Bit 2
(1)
PBADEN
Bit 1
TRISE1
TMR2MD
CCP2MD
T1RD16
T3RD16
T5RD16
TMR2IP
TMR3IP
CCP4IP
TMR2IE
TMR3IE
CCP4IE
TMR2IF
TMR3IF
CCP4IF
TRISC1
TRISD1
TRISA1
TRISB1
Bit 1
T1GSS
T3GSS
T5GSS
(1)
CCP2MX
DS41412D-page 183
TRISE0
Bit 0
TMR1MD
CCP1MD
TMR1ON
TMR3ON
TMR5ON
TMR1IP
TMR1IE
CCP2IP
CCP3IP
CCP2IE
CCP3IE
TMR1IF
CCP2IF
CCP3IF
TRISC0
TRISD0
TRISA0
TRISB0
Bit 0
(1)
Register
on Page
Register
on Page
354
127
128
130
123
124
126
121
170
171
170
171
170
171
154
154
154
154
154
118
119
56
57
—
—
—
—
—
—