PIC18F46K22-I/MV Microchip Technology, PIC18F46K22-I/MV Datasheet - Page 279

64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE

PIC18F46K22-I/MV

Manufacturer Part Number
PIC18F46K22-I/MV
Description
64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet

Specifications of PIC18F46K22-I/MV

Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 30x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-UFQFN Exposed Pad
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
4 KB
Number Of Programmable I/os
36
Number Of Timers
3 x 8-bit. 4 x 16-bit
Operating Supply Voltage
1.8 V to 5.5 V
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
16.3.1
The EUSART module supports automatic detection
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RXx signal, the RXx signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Setting the ABDEN bit of the BAUDCONx register
starts
(Section 16.3.2 “Auto-baud
ABD sequence takes place, the EUSART state
machine is held in Idle. On the first rising edge of the
receive line, after the Start bit, the SPBRGx begins
counting up using the BRG counter clock as shown in
Table
DTx pin at the end of the eighth bit period. At that time,
an accumulated value totaling the proper BRG period
is left in the SPBRGHx:SPBRGx register pair, the
ABDEN bit is automatically cleared, and the RCxIF
interrupt flag is set. A read operation on the RCREGx
needs to be performed to clear the RCxIF interrupt.
RCREGx
calibrating for modes that do not use the SPBRGHx
register the user can verify that the SPBRGx register
did not overflow by checking for 00h in the SPBRGHx
register.
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in
both the SPBRGHx and SPBRGx registers are used as
a 16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGHx
FIGURE 16-6:
 2010 Microchip Technology Inc.
RXx/DTx pin
BRG Value
BRG Clock
ABDEN bit
SPBRGHx
RCxIF bit
(Interrupt)
RCREGx
SPBRGx
16-6. The fifth rising edge will occur on the RXx/
RCIDL
Note 1:
Read
the
content
AUTO-BAUD DETECT
Set by User
The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
auto-baud
XXXXh
should
AUTOMATIC BAUD RATE CALIBRATION
Table
calibration
be
Overflow”). While the
0000h
discarded.
16-6. During ABD,
Start
sequence
bit 0
XXh
XXh
Edge #1
When
Preliminary
bit 1
bit 2
Edge #2
and SPBRGx registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
average bit time when clocked at full speed.
TABLE 16-6:
BRG16
Note:
Note 1: If the WUE bit is set with the ABDEN bit,
PIC18(L)F2X/4XK22
bit 3
0
0
1
1
2: It is up to the user to determine that the
3: During the auto-baud process, the auto-
bit 4
Edge #3
BRGH
During the ABD sequence, SPBRGx and
SPBRGHx registers are both used as a
16-bit counter, independent of BRG16
setting.
auto-baud detection will occur on the byte
following the Break character (see
Section 16.3.3
Break”).
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
baud counter starts counting at 1. Upon
completion of the auto-baud sequence, to
achieve maximum accuracy, subtract 1
from the SPBRGHx:SPBRGx register pair.
0
1
0
1
bit 5
BRG COUNTER CLOCK
RATES
BRG Base
bit 6
Edge #4
F
F
F
F
Clock
OSC
OSC
OSC
OSC
bit 7
/64
/16
/16
/4
“Auto-Wake-up
DS41412D-page 279
Stop bit
Edge #5
Auto Cleared
BRG ABD
001Ch
F
F
F
F
1Ch
00h
OSC
OSC
OSC
Clock
OSC
/512
/128
/128
/32
on

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