PIC18F46K22-I/MV Microchip Technology, PIC18F46K22-I/MV Datasheet - Page 385

• Manufacturer Part Number: PIC18F46K22-I/MV
• Description: 64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46K22-I/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-UFQFN Exposed Pad
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Number Of Programmable I/os: 36
• Number Of Timers: 3 x 8-bit. 4 x 16-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CPFSGT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2010 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
W
If REG
If REG
Q1
Q1
Q1
No
No
No
PC
PC
register ‘f’
operation
operation
operation
Compare f with W, skip if f > W
CPFSGT
0  f  255
a  [0,1]
(f) –W),
skip if (f) > (W)
(unsigned comparison)
None
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1(2)
Note: 3 cycles if skip and followed
HERE
NGREATER
GREATER
Read
0110
Q2
Q2
No
Q2
No
No
=
=

=

=
by a 2-word instruction.
Address (HERE)
?
W;
Address (GREATER)
W;
Address (NGREATER)
f {,a}
010a
CPFSGT REG, 0
:
:
operation
operation
operation
Process
Data
Q3
Q3
No
Q3
No
No
,
then the fetched
ffff
for details.
operation
operation
operation
operation
Q4
Q4
Q4
No
No
No
No
ffff
Preliminary
CPFSLT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
PIC18(L)F2X/4XK22
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
W
If REG
PC
If REG
PC
Q1
Q1
No
Q1
No
No
register ‘f’
operation
operation
operation
Compare f with W, skip if f < W
CPFSLT
0  f  255
a  [0,1]
(f) –W),
skip if (f) < (W)
(unsigned comparison)
None
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
1
1(2)
Note:
HERE
NLESS
LESS
Read
0110
Q2
Q2
No
Q2
No
No
=
=
<
=

=
3 cycles if skip and followed
by a 2-word instruction.
Address (HERE)
?
W;
Address (LESS)
W;
Address (NLESS)
CPFSLT REG, 1
:
:
f {,a}
000a
operation
operation
operation
Process
Data
Q3
Q3
No
Q3
No
No
DS41412D-page 385
ffff
operation
operation
operation
operation
Q4
Q4
Q4
No
No
No
No
ffff