EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 143

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
2.3.47
Freescale Semiconductor
Address 0x025A
Write: Anytime.
DDRP
DDRP
Field
Field
PTIP
Reset
7-0
6-0
7
W
R
Port P input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
Port P data direction—
This register controls the data direction of pin 7.
The enabled PWM channel 7 forces the I/O state to be an output. If the PWM shutdown feature is enabled this pin
is forced to be an input. In these cases the data direction bit will not change.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port P data direction—
The PWM forces the I/O state to be an output for each port line associated with an enabled PWM6-0 channel. In this
case the data direction bit will not change.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
DDRP7
Port P Data Direction Register (DDRP)
0
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTP or PTIP registers, when changing the
DDRP register.
DDRP6
0
6
Figure 2-45. Port P Data Direction Register (DDRP)
Table 2-43. DDRP Register Field Descriptions
Table 2-42. PTIP Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
DDRP5
0
5
DDRP4
NOTE
0
4
Description
Description
DDRP3
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
DDRP2
0
2
Access: User read/write
DDRP1
0
1
DDRP0
0
0
143
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