EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 182

Manufacturer Part Number

EVB9S12XEP100

BOARD EVAL FOR MC9S12XEP100

Manufacturer

Freescale Semiconductor

Module and Misc Hardware

Processor To Be Evaluated

MC9S12XEP100

Data Bus Width

Interface Type

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Rohs Compliant

For Use With/related Products

MC9S12XEP100

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 2 Port Integration Module (S12XEPIMV1)

This register configures the re-routing of SCI3, IIC0, CS[3:0] on alternative ports.

Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an

output from the external bus interface module or a peripheral module or an input to the external bus

interface module or a peripheral module.

A set of conﬁguration registers is common to all ports with exceptions in the expanded bus interface and

not become active.

This device does not become active while the port is used as a push-pull output.

Functional Description

2-103). All registers can be written at any time, however a speciﬁc conﬁguration might

MC9S12XE-Family Reference Manual , Rev. 1.23

Example 2-1. Selecting a pull-up device

Table 2-102. Port F Routing Summary

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