EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 492

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
The Sequence for clock quality check is shown in
1. A Clock Monitor Reset will always set the SCME bit to logical’1’.
492
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indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
POR
LVR
Remember that in parallel to additional actions caused by Self Clock Mode
or Clock Monitor Reset
check the OSCCLK signal.
The Clock Quality Checker enables the IPLL and the voltage regulator
(VREG) anytime a clock check has to be performed. An ongoing clock
quality check could also cause a running IPLL (f
during Pseudo Stop Mode.
CHECK WINDOW
CLOCK OK
OSC OK
ACTIVE?
NUM = 50
SCM
?
YES
NO
FSTWKP=1
SCME=1 &
NO
?
EXIT FULL STOP
NO
YES
Figure 11-18. Sequence for Clock Quality Check
CM FAIL
MC9S12XE-Family Reference Manual , Rev. 1.23
YES
1
SWITCH TO OSCCLK
handling the clock quality checker continues to
NUM = NUM-1
NUM = 0
EXIT SCM
NUM > 0
?
YES
NOTE
NOTE
Figure
NO
CLOCK MONITOR RESET
11-18.
ENTER SCM
ENTER SCM
YES
SCM
) and an active VREG
SCME = 1
ACTIVE?
SCM
?
NO
YES
FSTWKP = 0
NO
YES
?
Freescale Semiconductor
NO
NUM = 0