EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 721

Manufacturer Part Number

EVB9S12XEP100

BOARD EVAL FOR MC9S12XEP100

Manufacturer

Freescale Semiconductor

Module and Misc Hardware

Processor To Be Evaluated

MC9S12XEP100

Data Bus Width

Interface Type

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Rohs Compliant

For Use With/related Products

MC9S12XEP100

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the

corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order

bytes PWMEx bits have no effect and their corresponding PWM output is disabled.

In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or

high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by

16-bit access to maintain data coherency.

Freescale Semiconductor

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

Clock Source 7

Clock Source 5

Clock Source 3

Clock Source 1

MC9S12XE-Family Reference Manual Rev. 1.23

Figure 19-24. PWM 16-Bit Mode

Period/Duty Compare

Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)