EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 596

Manufacturer Part Number

EVB9S12XEP100

BOARD EVAL FOR MC9S12XEP100

Manufacturer

Freescale Semiconductor

Module and Misc Hardware

Processor To Be Evaluated

MC9S12XEP100

Data Bus Width

Interface Type

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Rohs Compliant

For Use With/related Products

MC9S12XEP100

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 15 Inter-Integrated Circuit (IICV3) Block Description

When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical

high), a master may initiate communication by sending a START signal.As shown in

START signal is deﬁned as a high-to-low transition of SDA while SCL is high. This signal denotes the

beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves

out of their idle states.

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

ADR7 ADR6 ADR5 ADR4ADR3 ADR2 ADR1R/W

ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1R/W

START Signal

Calling Address

START Condition

Calling Address

Figure 15-10. IIC-Bus Transmission Signals

MC9S12XE-Family Reference Manual , Rev. 1.23

Figure 15-11. Start and Stop Conditions

ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1R/W

New Calling Address

STOP Condition

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