EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 557

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

All bits reset to zero.
14.3.2.21 ICPAR — Input Control Pulse Accumulators Register (ICPAR)
Read: Anytime
Write: Anytime.
All bits reset to zero.
The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if PAEN in PACTL is cleared. If PAEN
is set, PA3EN and PA2EN have no effect.
The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if PBEN in PBCTL is cleared. If PBEN
is set, PA1EN and PA0EN have no effect.
Freescale Semiconductor
Module Base + 0x0028
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
POLF[3:0]
PA[3:0]EN
Reset
MCZF
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
Field
3:0
3:0
7
W
R
Modulus Counter Underflow Flag — The flag is set when the modulus down-counter reaches 0x0000.
The flag indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag clearing
mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA bit in
Section 14.3.2.6, “Timer System Control Register 1
First Input Capture Polarity Status — These are read only bits. Writes to these bits have no effect.
Each status bit gives the polarity of the first edge which has caused an input capture to occur after capture latch
has been read.
Each POLFx corresponds to a timer PORTx input.
0 The first input capture has been caused by a falling edge.
1 The first input capture has been caused by a rising edge.
8-Bit Pulse Accumulator ‘x’ Enable
0 8-Bit Pulse Accumulator is disabled.
1 8-Bit Pulse Accumulator is enabled.
0
0
7
When TFFCA = 1, the flag cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference
System Control Register 1
Figure 14-44. Input Control Pulse Accumulators Register (ICPAR)
= Unimplemented or Reserved
0
0
6
MC9S12XE-Family Reference Manual Rev. 1.23
Table 14-25. MCFLG Field Descriptions
Table 14-26. ICPAR Field Descriptions
5
0
0
(TSCR1)”.
NOTE
0
0
4
Description
Description
(TSCR1)”).
PA3EN
0
3
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Section 14.3.2.6, “Timer
PA2EN
2
0
PA1EN
0
1
PA0EN
0
0
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