EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 168

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.85
2.3.86
168
Function
Address 0x0368
Address 0x0369
Write: Anytime.
Write:Never, writes to this register have no effect.
Altern.
Field
Field
PTIR
Reset
PTR
Reset
7-0
7-0
W
W
R
R
TIMIOC7
Port R general purpose input/output data—Data Register
Port R pins 7 through 0 are associated with TIM channels TIMIOC7 through TIMIOC0.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port R input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
PTIR7
PTR7
Port R Data Register (PTR)
Port R Input Register (PTIR)
0
u
7
7
= Unimplemented or Reserved
TIMIOC6
PTIR6
PTR6
0
u
6
6
Table 2-82. PTIR Register Field Descriptions
Table 2-81. PTR Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 2-84. Port R Input Register (PTIR)
Figure 2-83. Port R Data Register (PTR)
TIMIOC5
PTIR5
PTR5
0
u
5
5
TIMIOC4
PTIR4
PTR4
0
u
4
4
Description
Description
u = Unaffected by reset
TIMIOC3
PTIR3
PTR3
3
0
3
u
TIMIOC2
PTIR2
PTR2
0
u
2
2
Access: User read/write
TIMIOC1
Freescale Semiconductor
PTIR1
PTR1
0
u
1
1
Access: User read
TIMIOC0
PTIR0
PTR0
0
u
0
0
(1)
(1)