EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 309

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.1.4
The S12XDBG module can be used in all MCU functional modes.
During BDM hardware accesses and whilst the BDM module is active, CPU12X monitoring is disabled.
Thus breakpoints, comparators, and CPU12X bus tracing are disabled but XGATE bus monitoring
accessing the S12XDBG registers, including comparator registers, is still possible. While in active BDM
or during hardware BDM accesses, XGATE activity can still be compared, traced and can be used to
generate a breakpoint to the XGATE module. When the CPU12X enters active BDM Mode through a
BACKGROUND command, with the S12XDBG module armed, the S12XDBG remains armed.
The S12XDBG module tracing is disabled if the MCU is secure. However, breakpoints can still be
generated if the MCU is secure.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Enable
BDM
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
•
•
•
•
•
x
0
0
1
1
External CPU12X instruction tagging trigger independent of comparators
XGATE S/W breakpoint request trigger independent of comparators
TRIG Immediate software trigger independent of comparators
Four trace modes
— Normal: change of flow (COF) PC information is stored (see
— Loop1: same as Normal but inhibits consecutive duplicate source address entries
— Detail: address and data for all cycles except free cycles and opcode fetches are stored
— Pure PC: All program counter addresses are stored.
4-stage state sequencer for trace buffer control
— Tracing session trigger linked to Final State of state sequencer
— Begin, End, and Mid alignment of tracing to trigger
flow definition.
Modes of Operation
Active
BDM
0
1
0
1
x
Secure
MCU
1
0
0
0
0
Table 8-3. Mode Dependent Restriction Summary
MC9S12XE-Family Reference Manual Rev. 1.23
Matches Enabled
Comparator
XGATE only
Yes
Yes
Yes
Active BDM not possible when not enabled
Breakpoints
XGATE only
Only SWI
Possible
Yes
Yes
Chapter 8 S12X Debug (S12XDBGV3) Module
Section
XGATE only
Possible
Tagging
Yes
Yes
Yes
8.4.5.2.1) for change of
XGATE only
Possible
Tracing
Yes
Yes
No
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