EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 617

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3.2.3
The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module.
1. Read: Anytime
Freescale Semiconductor
Module Base + 0x0002
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
SJW[1:0]
BRP[5:0]
SLPAK
INITAK
Field
Field
7-6
5-0
1
0
Reset:
W
R
Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see
Section 16.4.5.5, “MSCAN Sleep
Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will
clear the flag if it detects activity on the CAN bus while in sleep mode.
0 Running — The MSCAN operates normally
1 Sleep mode active — The MSCAN has entered sleep mode
Initialization Mode Acknowledge — This flag indicates whether the MSCAN module is in initialization mode
(see
mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1,
CANBTR0, CANBTR1, CANIDAC, CANIDAR0–CANIDAR7, and CANIDMR0–CANIDMR7 can be written only by
the CPU when the MSCAN is in initialization mode.
0 Running — The MSCAN operates normally
1 Initialization mode active — The MSCAN has entered initialization mode
Synchronization Jump Width — The synchronization jump width defines the maximum number of time quanta
(Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the
CAN bus (see
Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing
(see
MSCAN Bus Timing Register 0 (CANBTR0)
SJW1
Section 16.4.4.5, “MSCAN Initialization
Table
0
7
16-7).
Table 16-4. CANCTL1 Register Field Descriptions (continued)
Table
Figure 16-6. MSCAN Bus Timing Register 0 (CANBTR0)
SJW1
SJW0
Table 16-5. CANBTR0 Register Field Descriptions
0
0
1
1
6
0
16-6).
MC9S12XE-Family Reference Manual Rev. 1.23
Table 16-6. Synchronization Jump Width
BRP5
0
Mode”). It is used as a handshake flag for the SLPRQ sleep mode request.
5
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Mode”). It is used as a handshake flag for the INITRQ initialization
BRP4
SJW0
4
0
0
1
0
1
Description
Description
BRP3
0
3
Synchronization Jump Width
BRP2
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
2
0
1 Tq clock cycle
Access: User read/write
BRP1
0
1
BRP0
0
0
617
(1)