EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 666

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)
17.3.0.1
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
17.3.0.2
Read: Anytime
Write: Anytime
666
Module Base + 0x0000
Module Base + 0x0001
PFLMT[1:0]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
PITSWAI
PITFRZ
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
PITE
1:0
7
6
5
W
W
R
R
PFLT7
PITE
PIT Module Enable Bit — This bit enables the PIT module. If PITE is cleared, the PIT module is disabled and
flag bits in the PITTF register are cleared. When PITE is set, individually enabled timers (PCE set) start down-
counting with the corresponding load register values.
0 PIT disabled (lower power consumption).
1 PIT is enabled.
PIT Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.
0 PIT operates normally in wait mode
1 PIT clock generation stops and freezes the PIT module when in wait mode
PIT Counter Freeze while in Freeze Mode Bit — When during debugging a breakpoint (freeze mode) is
encountered it is useful in many cases to freeze the PIT counters to avoid e.g. interrupt generation. The PITFRZ
bit controls the PIT operation while in freeze mode.
0 PIT operates normally in freeze mode
1 PIT counters are stalled when in freeze mode
PIT Force Load Bits for Micro Timer 1:0 — These bits have only an effect if the corresponding micro timer is
active and if the PIT module is enabled (PITE set). Writing a one into a PFLMT bit loads the corresponding 8-bit
micro timer load register into the 8-bit micro timer down-counter. Writing a zero has no effect. Reading these bits
will always return zero.
Note: A micro timer force load affects all timer channels that use the corresponding micro time base.
PIT Control and Force Load Micro Timer Register (PITCFLMT)
PIT Force Load Timer Register (PITFLT)
0
0
0
7
7
Figure 17-3. PIT Control and Force Load Micro Timer Register (PITCFLMT)
= Unimplemented or Reserved
PITSWAI
PFLT6
0
0
0
6
6
Figure 17-4. PIT Force Load Timer Register (PITFLT)
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 17-2. PITCFLMT Field Descriptions
PITFRZ
PFLT5
5
0
5
0
0
PFLT4
0
0
0
0
4
4
Description
PFLT3
0
0
0
0
3
3
PFLT2
2
0
0
2
0
0
PFLMT1
Freescale Semiconductor
PFLT1
0
0
0
0
1
1
PFLMT0
PFLT0
0
0
0
0
0
0