EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 593

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

If it were the case that the IBSWAI bit was cleared when the WAI instruction was executed, the IIC internal
clocks and interface would remain alive, continuing the operation which was currently underway. It is also
possible to configure the IIC such that it will wake up the CPU via an interrupt at the conclusion of the
current operation. See the discussion on the IBIF and IBIE bits in the IBSR and IBCR, respectively.
15.3.1.4
This status register is read-only with exception of bit 1 (IBIF) and bit 4 (IBAL), which are software
clearable.
Freescale Semiconductor
RESERVED
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
IAAS
IBAL
TCF
IBB
7
6
5
4
3
W
R
Module Base + 0x0003
TCF
Data Transferring Bit — While one byte of data is being transferred, this bit is cleared. It is set by the falling
edge of the 9th clock of a byte transfer. Note that this bit is only valid during or immediately following a transfer
to the IIC module or from the IIC module.
0 Transfer in progress
1 Transfer complete
Addressed as a Slave Bit — When its own specific address (I-bus address register) is matched with the calling
address or it receives the general call address with GCEN== 1,this bit is set.The CPU is interrupted provided the
IBIE is set.Then the CPU needs to check the SRW bit and set its Tx/Rx mode accordingly.Writing to the I-bus
control register clears this bit.
0 Not addressed
1 Addressed as a slave
Bus Busy Bit
0 This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a STOP signal is
1 Bus is busy
Arbitration Lost — The arbitration lost bit (IBAL) is set by hardware when the arbitration procedure is lost.
Arbitration is lost in the following circumstances:
This bit must be cleared by software, by writing a one to it. A write of 0 has no effect on this bit.
Reserved — Bit 3 of IBSR is reserved for future use. A read operation on this bit will return 0.
IIC Status Register (IBSR)
1
7
detected, IBB is cleared and the bus enters idle state.
1. SDA sampled low when the master drives a high during an address or data transmit cycle.
2. SDA sampled low when the master drives a high during the acknowledge bit of a data receive cycle.
3. A start cycle is attempted when the bus is busy.
4. A repeated start cycle is requested in slave mode.
5. A stop condition is detected when the master did not request it.
IAAS
= Unimplemented or Reserved
0
6
Figure 15-7. IIC Bus Status Register (IBSR)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 15-9. IBSR Field Descriptions
IBB
5
0
IBAL
0
4
Description
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
0
0
3
SRW
2
0
IBIF
0
1
RXAK
0
0
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