EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 61

BOARD EVAL FOR MC9S12XEP100

EVB9S12XEP100

Manufacturer Part Number
EVB9S12XEP100
Description
BOARD EVAL FOR MC9S12XEP100
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of EVB9S12XEP100

Contents
Module and Misc Hardware
Processor To Be Evaluated
MC9S12XEP100
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12XE
Rohs Compliant
Yes
For Use With/related Products
MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Freescale Semiconductor
Function 1
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
PR[7:0]
PT[7:6]
PT[4:0]
Name
PT[5]
PP4
PP3
PP2
PP1
PP0
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Pin
Function 2
IOC[7:6]
IOC[4:0]
TIMIOC
MOSI0
MISO0
IOC[5]
Name
KWP4
KWP3
KWP2
KWP1
KWP0
SCK0
RXD1
RXD0
TXD1
TXD0
[7:0]
SS0
Pin
Function 3
VREGAPI
PWM4
PWM3
PWM2
PWM1
PWM0
Name
Pin
Table 1-10. Signal Properties Summary (Sheet 4 of 4)
MC9S12XE-Family Reference Manual Rev. 1.23
Function 4
MISO2
MOSI1
MISO1
Name
SCK1
SS1
Pin
Function 5
TIMIOC4
TIMIOC3
TIMIOC2
TIMIOC1
TIMIOC0
Name
Pin
Supply
Power
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
PERR/
PERP/
PERP/
PERP/
PERP/
PERP/
PERS/
PERS/
PERS/
PERS/
PERS/
PERS/
PERS/
PERS/
PERT/
PERT/
PERT/
CTRL
PPSP
PPSP
PPSP
PPSP
PPSP
PPSR
PPSS
PPSS
PPSS
PPSS
PPSS
PPSS
PPSS
PPSS
PPST
PPST
PPST
Internal Pull
Resistor
Chapter 1 Device Overview MC9S12XE-Family
Disabled Port P I/O, interrupt, channel
Disabled Port P I/O, interrupt, channel
Disabled Port P I/O, interrupt, channel
Disabled Port P I/O, interrupt, channel
Disabled Port P I/O, interrupt, channel
Disabled Port RI/O, TIM channels
Disabled Port T I/O, ECT channels
Disabled Port T I/O, ECT channels
Disabled Port T I/O, ECT channels
Reset
State
Up
Up
Up
Up
Up
Up
Up
Up
4 of PWM/TIM, MISO2 of
SPI2
3 of PWM/TIM, SS of SPI1
2 of PWM/TIM, SCK of SPI1
1 of PWM/TIM, MOSI of
SPI1
0 of PWM/TIM, MISO2 of
SPI1
Port S I/O, SS of SPI0
Port S I/O, SCK of SPI0
Port S I/O, MOSI of SPI0
Port S I/O, MISO of SPI0
Port S I/O, TXD of SCI1
Port S I/O, RXD of SCI1
Port S I/O, TXD of SCI0
Port S I/O, RXD of SCI0
Description
61

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