EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 161

Manufacturer Part Number

EVB9S12XEP100

BOARD EVAL FOR MC9S12XEP100

Manufacturer

Freescale Semiconductor

Module and Misc Hardware

Processor To Be Evaluated

MC9S12XEP100

Data Bus Width

Interface Type

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Rohs Compliant

For Use With/related Products

MC9S12XEP100

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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1. Read: Anytime.

Freescale Semiconductor

Address 0x0274

Write: Anytime.

Port AD0 data direction—

This register controls the data direction of pins 7 through 0.

1 Associated pin is conﬁgured as output.

0 Associated pin is conﬁgured as input.

Port AD0 reduced drive—Select reduced drive for Port AD0 outputs

This register conﬁgures the drive strength of Port AD0 output pins 15 through 8 as either full or reduced independent

of the function used on the pins. If a pin is used as input this bit has no effect.

1 Reduced drive selected (approx. 1/5 of the full drive strength).

0 Full drive strength enabled.

Port AD0 Reduced Drive Register 0 (RDR0AD0)

Due to internal synchronization circuits, it can take up to 2 bus clock cycles

until the correct value is read on PT0AD0 registers, when changing the

DDR1AD0 register.

To use the digital input function on Port AD0 the ATD Digital Input Enable

Figure 2-71. Port AD0 Reduced Drive Register 0 (RDR0AD0)

Table 2-68. DDR1AD0 Register Field Descriptions

Table 2-69. RDR0AD0 Register Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

Chapter 2 Port Integration Module (S12XEPIMV1)

Access: User read/write

EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 161

EVB9S12XEP100

Specifications of EVB9S12XEP100

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