EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 38

Manufacturer Part Number

EVB9S12XEP100

BOARD EVAL FOR MC9S12XEP100

Manufacturer

Freescale Semiconductor

Module and Misc Hardware

Processor To Be Evaluated

MC9S12XEP100

Data Bus Width

Interface Type

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Rohs Compliant

For Use With/related Products

MC9S12XEP100

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 1 Device Overview MC9S12XE-Family

Block B1 is divided into two 128K blocks. The XGATE is always mapped to block B1S.

On the 9S12XEG128 the ﬂash is divided into two 64K blocks B0 and B1S, the B1S range extending from

0x78_0000 to 0x78_FFFF, the B0 range extending from 0x7F_0000 to 0x7F_FFFF.

The block B0 is a reduced size 128K block on the 256K derivative. On the larger derivatives B0 is a 256K

block. The block B0 is a reduced size 64K block on the 128K derivative.

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

1. The 9S12XEA devices are special bondouts for access to extra ADC channels in 80QFP.

Available in 80QFP only. WARNING: NOT PIN-COMPATIBLE WITH REST OF FAMILY.

Table 1-5. Derivative Dependent Flash Block Mapping (continued)

MC9S12XE-Family Reference Manual , Rev. 1.23

Freescale Semiconductor