EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 247

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Refer to the S12X_MMC section for a detailed description of the MCU operating modes.
5.1.4
Figure 5-1
5.2
The user is advised to refer to the SoC section for port configuration and location of external bus signals.
Table 5-2
and PIM section for reset states of these pins and associated pull-ups or pull-downs.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
External Signal Description
outlines the pin names and gives a brief description of their function. Refer to the SoC section
is a block diagram of the XEBI with all related I/O signals.
Block Diagram
The following external bus related signals are described in other sections:
ECLK, ECLKX2 (free-running clocks) — PIM section
TAGHI, TAGLO (tag inputs) — PIM section, S12X_DBG section
EWAIT
MC9S12XE-Family Reference Manual Rev. 1.23
Figure 5-1. XEBI Block Diagram
XEBI
NOTE
Chapter 5 External Bus Interface (S12XEBIV4)
ADDR[22:0]
DATA[15:0]
IVD[15:0]
LSTRB
RW
UDS
LDS
RE
WE
ACC[2:0]
IQSTAT[3:0]
CS[3:0]
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