EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 314

BOARD EVAL FOR MC9S12XEP100

EVB9S12XEP100

Manufacturer Part Number
EVB9S12XEP100
Description
BOARD EVAL FOR MC9S12XEP100
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of EVB9S12XEP100

Contents
Module and Misc Hardware
Processor To Be Evaluated
MC9S12XEP100
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12XE
Rohs Compliant
Yes
For Use With/related Products
MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 8 S12X Debug (S12XDBGV3) Module
8.3.2.2
Read: Anytime
Write: Never
314
Address: 0x0021
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
SSF[2:0]
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
EXTF
Field
POR
TBF
2–0
7
6
W
R
TBF
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits CNT[6:0].
The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset
initialization. Other system generated resets have no affect on this bit
External Tag Hit Flag — The EXTF bit indicates if a tag hit condition from an external TAGHI/TAGLO tag was
met since arming. This bit is cleared when ARM in DBGC1 is written to a one.
0 External tag hit has not occurred
1 External tag hit has occurred
State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During
a debug session on each transition to a new state these bits are updated. If the debug session is ended by
software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer
before disarming. If a debug session is ended by an internal trigger, then the state sequencer returns to state0
and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state
sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See
Debug Status Register (DBGSR)
0
7
= Unimplemented or Reserved
EXTF
Table 8-9. SSF[2:0] — State Sequence Flag Bit Encoding
0
0
6
101,110,111
Figure 8-4. Debug Status Register (DBGSR)
SSF[2:0]
MC9S12XE-Family Reference Manual , Rev. 1.23
000
001
010
011
100
Table 8-8. DBGSR Field Descriptions
5
0
0
0
0
0
0
4
Description
State0 (disarmed)
Current State
Final State
Reserved
0
0
0
3
State1
State2
State3
SSF2
Table 8-9
2
0
0
.
Freescale Semiconductor
SSF1
0
0
1
SSF0
0
0
0

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